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Altera_Forum
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16 years ago

A problem with using DCFIFO (lpm_fifo)

Hello! In my design I have a 8bit x 4 words dual-clock fifo component (LPM_FIFO+) and I observe a very strange behaviour or the wrfull output signal. Since I have fifo 4 word-deep I expect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The rdclk is there as well, it is much slower frequency and it is not visible on the simulation fragment.

The fifo component works in the TX part of the uart circuit.

The wrclk is the CPU clock, very fast compared to the rxclk, which is the baud clock.

Whole CPU write cycle happens between edges of the baud clock (rdclk).

Is there any restrictions on frequency difference between these two clocks?

Also, what is strange, I got the sample waveforms from this component and they not look good:

http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view&current=uart_lpm_fifo_tx3_wave0.jpg

This is 4 words fifo and the wrfull goes already high after 3rd wrclk edge during write sequence... This sample waveform is wrong or I am missing something? What is going on?