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Honored Contributorwriting/reading sram with cyclone3 in vhdl
Hey,
i'm trying to write and read to/from the sram with a cyclone3 fpga on a NEEK. I wrote a little code to check if it's working, but it doesn't and i tried very much around but to no avail. The clk input is driven by a pll with 100Mhz (of course i connected the SRAM_clk to it). I changed the configuration scheme to passive serial to use DATA[0] and DATA[1] as regular IO-pins. So here's the code, maybe someone will notice a mistake i haven't come across.library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity videosync is
port (clk, nRst: in std_logic;
data: inout std_logic_vector(31 downto 0);
addr: out std_logic_vector(20 downto 0);
nCS, nOE, nWE: out std_logic;
nadsc, nbe0, nbe1, nbe2, nbe3: out std_logic;
led0, led1, led2, led3: out std_logic;
flashnOE, flashnCE: out std_logic);
end entity videosync;
architecture behave of videosync is
-- readram signals
type ramState is (write, read);
signal ramst : ramState;
signal ramcount: integer := 0;
signal notWE: std_logic;
signal memoryData: std_logic_vector(31 downto 0);
begin
readram_process: process (clk, nRst) is
begin
if nRst = '0' then
flashnOE <= '1';
flashnCE <= '1';
nadsc <= '1';
nbe0 <= '1';
nbe1 <= '1';
nbe2 <= '1';
nbe3 <= '1';
led0 <= '1';
led1 <= '1';
led2 <= '1';
led3 <= '1';
nCS <= '0';
nOE <= '1';
notWE <= '1';
addr <= (others => '0');
memoryData <= (others => '0');
ramcount <= 0;
ramst <= write;
elsif rising_edge(clk) then
case ramst is
when write =>
if ramcount = 0 then
addr <= std_logic_vector(to_unsigned(ramcount, 21));
memoryData <= "11111111000000000000000000000000";
nadsc <= '0';
ramcount <= ramcount + 1;
elsif ramcount = 1 then
notWE <= '0';
nadsc <= '1';
ramcount <= ramcount + 1;
elsif ramcount = 2 then
notWE <= '1';
addr <= (others => '0');
ramcount <= ramcount + 1;
else
ramcount <= 0;
ramst <= read;
end if;
when read =>
if ramcount = 0 then
addr <= std_logic_vector(to_unsigned(0, 21));
nadsc <= '0';
ramcount <= ramcount + 1;
elsif ramcount = 1 then
nOE <= '0';
nadsc <= '1';
if data = "11111111000000000000000000000000" then
led0 <= '0';
else
led0 <= '1';
end if;
ramcount <= ramcount + 1;
elsif ramcount = 2 then
if data = "11111111000000000000000000000000" then
led1 <= '0';
else
led1 <= '1';
end if;
ramcount <= ramcount + 1;
elsif ramcount = 3 then
if data = "11111111000000000000000000000000" then
led2 <= '0';
else
led2 <= '1';
end if;
ramcount <= ramcount + 1;
nadsc <= '1';
addr <= (others => '0');
nOE <= '1';
else
null;
end if;
end case;
end if;
end process readram_process;
nWE <= '0' when notWE = '0' else '1';
data <= memoryData when notWE = '0' else (others => 'Z');
end architecture behave;24 Replies
Altera_Forum--- Quote Start --- i don't get, why SRAM_clk is always '1' --- Quote End --- You're acquiring a 100 MHz clk with a 100 MHz sampling clock, what do you expect... You didn't mention the involved chip type, but the RAM signals don't look like correct SSRAM control.- Altera_Forum--- Quote Start --- You didn't mention the involved chip type, but the RAM signals don't look like correct SSRAM control. --- Quote End --- What do you mean by that? I used all signals i found for the SSRAM in the cycloneIII reference manual or do you mean the timing and values of the signals? If so, would you mind correcting them? At the time when i took the screenshots (and wondered why SRAM_clk is always '1') my sampling clock was running at 50Mhz by accidence, as i stated in my last post. EDIT: oh wait, then of course it can't be otherwise too, because it's even slower... sorry, my bad :rolleyes: I also forgot the chip type, it's the ISSI IS61LPS25636A-200TQLI on the NEEK.
- Altera_Forum
Because you don't show all SSRAM controls signals, I can't say, if there are more errors. But nCS and nWE respectively nOE have to be activated simultaneously, but you do sequentially.
P.S.: Sorry, I see that the control signal is nADV, which has to be activated in front of read and write. Can youe tell about the state of the other control signals? - Altera_Forum
Ah, now i know what you mean.
The other control signals are not accessible with the cycloneIII. nADV, nADSP, CE2, ZZ and MODE are hardwired i guess (at least it looks like that in the cycloneIII schematic). In the cycloneIII reference manual there are only the signals i used, so i think it's possible to use the SSRAM only with them P.S: i also tried activating nCS and nWE/nOE simultaneously, but i got the same result. do i need the signals nADV, nADSP or nADSC to perform a single write/read? i thought they are used to perform burst operations - Altera_Forum
Yes the numbers are clock cycles. If you can, try to regroup the address signals together. Then you'll get a single line with the address in hexadecimal form. You can do the same thing with the data.
I think that you need to hold oen low for several cycles. The be_n* signals should also be low when you write. They are used to select which bytes to write in the 32-bit word. - Altera_Forum--- Quote Start --- The be_n* signals should also be low when you write. --- Quote End --- Very true. It's a sufficient reason to make the test fail. If it still doesn't work, can you show a Signaltap recording with better time resolution? It's possible to generate a higher frequency sampling clock (e.g. 200 MHz) to see the bus signal timing.
- Altera_Forum
Here you are. Hopefully you will find something, because i just don't get it why it shouldn't work :|
- Altera_Forum
I wonder, if SRAM_DATA (I guess, the top entity port) is correctly wired to memory_data?
To check the RAM operation, a sequence like below should be performed: write data xx to address 1 write data yy to address 2 read from address 1 read from address 2 - Altera_Forum
That was a pretty good idea, i think. As you can see, the data bus just changes the first 16 bits and the output enable doesn't even work at all (the sram doesn't put anything on the bus). I don't know why this happens though, maybe you got an idea? I tried the sequence two times with nADSC enabled before read/write operations and without it and it doesn't change anything.
- Altera_Forum
Did you change your code a lot since the first post? because both "data" and "memorydata" (from the first code) should be exactly the same when we_n is '0' (with at most one sample clock delay) but it doesn't seem to be the case. Are you sure you are looking at the right data signals?
