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Altera_Forum
Honored Contributor
Honored Contributorwriting/reading sram with cyclone3 in vhdl
Hey, i'm trying to write and read to/from the sram with a cyclone3 fpga on a NEEK. I wrote a little code to check if it's working, but it doesn't and i tried very much around but to no avail. The ...
Altera_ForumHonored Contributor
Honored ContributorDid you change your code a lot since the first post? because both "data" and "memorydata" (from the first code) should be exactly the same when we_n is '0' (with at most one sample clock delay) but it doesn't seem to be the case. Are you sure you are looking at the right data signals?
