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Altera_Forum's avatar
Altera_Forum
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15 years ago

writing/reading sram with cyclone3 in vhdl

Hey, i'm trying to write and read to/from the sram with a cyclone3 fpga on a NEEK. I wrote a little code to check if it's working, but it doesn't and i tried very much around but to no avail. The ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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You didn't mention the involved chip type, but the RAM signals don't look like correct SSRAM control.

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What do you mean by that? I used all signals i found for the SSRAM in the cycloneIII reference manual or do you mean the timing and values of the signals? If so, would you mind correcting them?

At the time when i took the screenshots (and wondered why SRAM_clk is always '1') my sampling clock was running at 50Mhz by accidence, as i stated in my last post.

EDIT: oh wait, then of course it can't be otherwise too, because it's even slower... sorry, my bad :rolleyes:

I also forgot the chip type, it's the ISSI IS61LPS25636A-200TQLI on the NEEK.