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Honored Contributor
Honored Contributorwriting/reading sram with cyclone3 in vhdl
Hey, i'm trying to write and read to/from the sram with a cyclone3 fpga on a NEEK. I wrote a little code to check if it's working, but it doesn't and i tried very much around but to no avail. The ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The be_n* signals should also be low when you write. --- Quote End --- Very true. It's a sufficient reason to make the test fail. If it still doesn't work, can you show a Signaltap recording with better time resolution? It's possible to generate a higher frequency sampling clock (e.g. 200 MHz) to see the bus signal timing.
