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Altera_Forum's avatar
Altera_Forum
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15 years ago

writing/reading sram with cyclone3 in vhdl

Hey, i'm trying to write and read to/from the sram with a cyclone3 fpga on a NEEK. I wrote a little code to check if it's working, but it doesn't and i tried very much around but to no avail. The ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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i don't get, why SRAM_clk is always '1'

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You're acquiring a 100 MHz clk with a 100 MHz sampling clock, what do you expect...

You didn't mention the involved chip type, but the RAM signals don't look like correct SSRAM control.