Forum Discussion

Vandana_GS's avatar
Vandana_GS
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Unable to generate output for 32bit real and imaginary data in hardware implementation for Agilex 7

Hi,

I'm trying to do the hardware Implementation for a complex code containing real and imaginary 32 bits. I have two LED PIN options in the agilex board: Terasic Agilex SOM Module FPGA: Agilex AGFB014R24B2E2V . Is it necessary to assign the output LED Pins or any other alternative option is there to assign the pins. In the Questa simulation output is generated correctly. but while performing hardware implementation the output is not matching.

1. The error is appearing in the MSB four bits. Below is the simulated output:

2. Below is the hardware-implemented output as seen in signal tap analyzer:

Could you please suggest how we can proceed further?
Thanks & Regards
Vandana G S
Board Debug

12 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Without seeing any code of what the design is trying to do, there's really no way to help here.

    And can you clarify/highlight what is wrong with the Signal Tap output vs. the simulation?

    • Vandana_GS's avatar
      Vandana_GS
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi,

      Thank you for the response. I will not be able to share the design file in the community. During the simulation the outputs are generated correctly as expected.

      Simulaton output matches the following requirement:

      32'h5A:begin treal=32'h0; timag=32'h3F800000;end//90 degree
      32'h10E:begin treal=32'h0; timag=32'hBF800000;end//270degree
      32'h168:begin treal=32'h3F800000; timag=32'h0;end//360 degree
      32'h21C:begin treal=32'hBF800000; timag=32'h0;end//540 degree
      32'h32A:begin treal=32'h0; timag=32'h3F800000;end//810 degree

      In the hardware implementation imaginary values are appearing correctly but real values are incorrect i.e., 3F800000 is replaced by 1F800000 and BF800000 is replaced by 5F800000. The problem is appearing in the MSB of the real data.

      The pin planner used for the design is provided in the txt file attached along with the post.

      Thank you,

      Vandana

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    This doesn't really help. Without seeing code, there is no way to understand why bits are getting flipped when you don't expect it. I/O pin selection doesn't really matter here.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    I run the code on Cyclone 10LP test board (Trenz CYC1000) and get same result as in simulation. Recorded with 12 MHz clk and Power-Up Trigger. There might a timing problem in your hardware test.

    • Vandana_GS's avatar
      Vandana_GS
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi,

      As I am new to hardware programming could you please explain in detail. What could be the timing problem? Our FPGA has frequency clock of 50MHz.

      Thank you

      Vandana

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    does the design pass timing analysis?

    • Vandana_GS's avatar
      Vandana_GS
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi,

      Yes. it has passed timing analysis

      Thank you

      Vandana G S

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    It's not clear how your signaltap is trigerred and which acquisition is used. May be data are simply sampled at the wrong time.

    • Vandana_GS's avatar
      Vandana_GS
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi,

      Since I am beginner using Quartus Prime software. please explain the procedure to signal tap trigger and performing acqusition. This will help in properly excuting the hardware implementation.

      Thank you

      Vandana

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    You may view the Signal Tap training video here:

    https://learning.intel.com/Developer/learn/learning-plans/245/using-the-signal-tap-logic-analyzer


    Additionally, you can refer to the Application Note on how to use it:

    https://www.intel.com/content/www/us/en/design-example/815955/intel-arria-10-fpga-signal-tap-logic-analyzer-getting-started-design-example.html?wapkw=Signal%20Tap%20Logic%20Analyzer%3A%20%22Introduction%22%20%26%20Getting%20Started


    Regards,

    Richard Tan


  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Thank you for acknowledging the solution provided.


    Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.

    Thank you and have a great day!

    Best Regards,

    Richard Tan