Forum Discussion
Vandana_GS
New Contributor
New ContributorUnable to generate output for 32bit real and imaginary data in hardware implementation for Agilex 7
Hi, I'm trying to do the hardware Implementation for a complex code containing real and imaginary 32 bits. I have two LED PIN options in the agilex board: Terasic Agilex SOM Module FPGA: Agilex AGF...
You may view the Signal Tap training video here:
https://learning.intel.com/Developer/learn/learning-plans/245/using-the-signal-tap-logic-analyzer
Additionally, you can refer to the Application Note on how to use it:
Regards,
Richard Tan
FvM
Super Contributor
Super ContributorHi,
I run the code on Cyclone 10LP test board (Trenz CYC1000) and get same result as in simulation. Recorded with 12 MHz clk and Power-Up Trigger. There might a timing problem in your hardware test.
Vandana_GSNew Contributor
New ContributorHi,
As I am new to hardware programming could you please explain in detail. What could be the timing problem? Our FPGA has frequency clock of 50MHz.
Thank you
Vandana
