Forum Discussion
Vandana_GS
New Contributor
New ContributorUnable to generate output for 32bit real and imaginary data in hardware implementation for Agilex 7
Hi, I'm trying to do the hardware Implementation for a complex code containing real and imaginary 32 bits. I have two LED PIN options in the agilex board: Terasic Agilex SOM Module FPGA: Agilex AGF...
You may view the Signal Tap training video here:
https://learning.intel.com/Developer/learn/learning-plans/245/using-the-signal-tap-logic-analyzer
Additionally, you can refer to the Application Note on how to use it:
Regards,
Richard Tan
FvM
Super Contributor
Super ContributorHi,
It's not clear how your signaltap is trigerred and which acquisition is used. May be data are simply sampled at the wrong time.
Vandana_GSHi,
Since I am beginner using Quartus Prime software. please explain the procedure to signal tap trigger and performing acqusition. This will help in properly excuting the hardware implementation.
Thank you
Vandana
