Forum Discussion
New ContributorUnable to generate output for 32bit real and imaginary data in hardware implementation for Agilex 7
You may view the Signal Tap training video here:
https://learning.intel.com/Developer/learn/learning-plans/245/using-the-signal-tap-logic-analyzer
Additionally, you can refer to the Application Note on how to use it:
Regards,
Richard Tan
Super ContributorWithout seeing any code of what the design is trying to do, there's really no way to help here.
And can you clarify/highlight what is wrong with the Signal Tap output vs. the simulation?
Vandana_GSHi,
Thank you for the response. I will not be able to share the design file in the community. During the simulation the outputs are generated correctly as expected.
Simulaton output matches the following requirement:
32'h5A:begin treal=32'h0; timag=32'h3F800000;end//90 degree
32'h10E:begin treal=32'h0; timag=32'hBF800000;end//270degree
32'h168:begin treal=32'h3F800000; timag=32'h0;end//360 degree
32'h21C:begin treal=32'hBF800000; timag=32'h0;end//540 degree
32'h32A:begin treal=32'h0; timag=32'h3F800000;end//810 degreeIn the hardware implementation imaginary values are appearing correctly but real values are incorrect i.e., 3F800000 is replaced by 1F800000 and BF800000 is replaced by 5F800000. The problem is appearing in the MSB of the real data.
The pin planner used for the design is provided in the txt file attached along with the post.
Thank you,
Vandana
