Forum Discussion

Icon for New Contributor rank

New Contributor

1 year ago

Solved

Unable to generate output for 32bit real and imaginary data in hardware implementation for Agilex 7

Hi, I'm trying to do the hardware Implementation for a complex code containing real and imaginary 32 bits. I have two LED PIN options in the agilex board: Terasic Agilex SOM Module FPGA: Agilex AGF...

RichardT_altera
1 year ago
You may view the Signal Tap training video here:
https://learning.intel.com/Developer/learn/learning-plans/245/using-the-signal-tap-logic-analyzer

Additionally, you can refer to the Application Note on how to use it:
https://www.intel.com/content/www/us/en/design-example/815955/intel-arria-10-fpga-signal-tap-logic-analyzer-getting-started-design-example.html?wapkw=Signal%20Tap%20Logic%20Analyzer%3A%20%22Introduction%22%20%26%20Getting%20Started

Regards,
Richard Tan

Icon for Super Contributor rank

Super Contributor

1 year ago

Hi,
does the design pass timing analysis?

Icon for New Contributor rank

New Contributor

1 year ago

Hi,

Yes. it has passed timing analysis

Thank you

Vandana G S