Hi,Im officially out of luck. After wasting an entire week on trying to get the programmer to work I posting my question within this forum. I've got multiple bit stream files I'd like to use for configuration of our agilex FPGA (AGFB014R24A2E3VR0). While the UBII and Power Max 10 chips do seam to work (the board test system shows power and clock stats) the programming (both our bitstream and the intel example bitstreams) always fails at 13% (using both the quartus programmer and the one provided by the BTS). Searching the exact error message (obtained by right click -> copy on the log message) wasn't of any help. We're using Quartus Pro 20.4 on Ubuntu 20 and Windows 10 (neither worked, both with the same issue). Please review the attached screen shot for further details.

Hi, thanks a lot for your help! We've fixed this issue now. One thing we'd like to share, for a potential future reader, is that in addition to the above mentioned article one needs to completely erase the flash prior to configuring. Our working solutions looks like the following: Power off the board. Waiting for the caps to be drained doesn't seam to be necessary. Set MSEL[2:0] to ON/OFF/OFF Power on the board. Erase the boards flash using the programmer tools Power off the board. Set MSEL[2:0] to OFF/OFF/OFF Power on the board Programm your *.sof file. It's also required to leave the JTAG chain in the default configuration while erasing the flash. Last but not least: If step 8 fails retry a couple of times until it stops failing (we usually don't need more than 3 tries). It also seams to be more reliable (programming fails less often) at 24MHz than 6MHz, which the programmer defaults to anyway.

Intel Agilex F-Series dev kit cant be programmed by JTAG

26 Replies

YuanLi_S_Intel
Regular Contributor
5 years ago
Hi
I suspect your TCK frequency might be the root cause here.
Can you kindly try to reduce your TCK frequency to 6 MHz (default value)?
Below link is the command to change TCK frequency (on page 14= "2.8. Changing the TCK Frequency")
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr_ii_cable.pd...
Kindly try it out with your design and let me know the result.
Thanks
- leondietrich
  Occasional Contributor
  5 years ago
  Hi, thanks for your answer. We already tried 1MHz, 6MHz, 12MHz, 24MHz both by changing it within the GUI and the command line tools (al dough we didn't tried 12MHz on Ubuntu). Unfortunately none of these combinations worked.
YuanLi_S_Intel
Regular Contributor
5 years ago
Hi,

Can you check the following?
Have you tried to program the agilex with a simple design with SOF bitstream?

Thank You
- leondietrich
  Occasional Contributor
  5 years ago
  Hi, Thanks for your help! We've also tried to configure the FPGA with an SOF bitstream, reassembling a fairly simple (a 4 bit shift register enabling one QSFP and GPIO led at a time, powered by a clock divider in order to make the blinking human visible, the HDL code itself is known to be working). We've also tried the sof bitstreams provided by the example projects. None of those worked either.
- leondietrich
  Occasional Contributor
  5 years ago
  I don't know if it's relevant but we're getting the following warning when trying to program said test-bitstream (which I've attached to this message for reference purposes):
  
  Warning(19729): Current CMF data structure hash (0x15CD440C) is older version than latest CMF data structure but still allowable.
  This might be transition period. You should update your CMF to latest version with hash { 0x8AC9CBBA } [ACDS 20.4 Release]
  Hello_World.tar.xz59 KB
  - dsigner
    New Contributor
    4 years ago
    I observe the Warning(19729) as well.
YuanLi_S_Intel
Regular Contributor
4 years ago
Hi,

May i know which SOF bitstream you are using in the design example? Can you create a simple SOF file with simple input and output initialization and program and see?

Meanwhile for the warning message regarding to CMF, it can be safely ignored.
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2020/warning--19729---current-cmf-data-structure-hash--0xa2c420ac--is0.html

Thank You.

Regards,
bruce
- leondietrich
  Occasional Contributor
  4 years ago
  Hi,
  
  from the BTS we've tried bts_config.sof and qsfpdd_xcvr_nrz_25gbps.sof as well as the GPIO example. The Bitstream we've provided above (Have a look inside Hello_World.tar.xz), initializes the I/O and toggles the GPIO and QSFP leds at 1Hz. Besides writing a bitstream generated by the golden top example, I'm out of Ideas what could be more simple.
  
  Also I observed that sometimes, the first JTAG timeout error message occures prior to the 209060 message indicating the start of the programming process.
YuanLi_S_Intel
Regular Contributor
4 years ago
Hi,

Can you share me the screenshot of the Quartus programmer?

Also, what is the device part number used in the quartus design?

Thank You.

Regards,
Bruce
- leondietrich
  Occasional Contributor
  4 years ago
  We're using the AGFB014R24A2E3VR0 part as stated on the sticker on our dev kit. Since our last post we downgraded to Quartus 19.1 and get a different error since then (Error(18952): Error status: Synchronization failed). I've attached a recent screenshot as requested.
YuanLi_S_Intel
Regular Contributor
4 years ago
Can you try to use the previous programmer version that you are using? Also, try to remove the other devices in the JTAG chain and remain only the agilex.
- leondietrich
  Occasional Contributor
  4 years ago
  Hi, Do you mean Quartus 20 with "previous programmer version"? Also, according to the documentation provided by Intel the second device in the chain (the MAX 10 fpga) can't be removed from the chain. All other available DIP switches only add further devices to the JTAG chain.
dsigner
New Contributor
4 years ago
I'm observing the exact same problem on two (out of two) boards.

Our boards are based upon the AGFB014R24A2E2VR0 device.

The result is the same with a very simple LED flashing design as with a design downloaded from:

https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/agilex/f-fpga/agilexfb_agfb014r24a2e2vr0_fpga_en_reva_v20.4b72_v1.0.zip

For example:
agilexfb_agfb014r24a2e2vr0_fpga_en_reva_v20.4b72_v1.0/examples/pcie_gen4/pcie_gen4_ep_ed.sof

Setting DEVICE_INITIALIZATION_CLOCK INIT_INTOSC does not change the result.

It fails at different TCK speeds, including 6MHz.

Running thousands of IDCODE cycles reports no problems.

Using an external USB Blaster (TerASIC) results in the exact same error messages.

I'm running Quartus Programmer Pro v20.4.0.72 under Ubuntu 18.4

I have no problems loading a sof on a CycloneV SoC board using the same host and SW.

All DIP switches settings are as when the boards were received and according to the default values in the user guide at:
https://www.intel.com/content/www/us/en/programmable/documentation/zbg1567202330317.html

I always get the error:

Error (18950): Device has stopped receiving configuration data
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18947): Device not responding
Error (209012): Operation failed

the first time after power cycle of the board. Then any subsequent programming operations results in:

Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18952): Error status: Synchronization failed
Error (209012): Operation failed
YuanLi_S_Intel
Regular Contributor
4 years ago
Hi Leon,

Can you try to change SW1.1 to ON as per suggested? Any update on this?
- leondietrich
  Occasional Contributor
  4 years ago
  Hi,
  
  I'll be in office tomorrow and will report my results here.
- leondietrich
  Occasional Contributor
  4 years ago
  Hi, As requested I checked if setting SW1.1 to ON is improving anything. The only difference it made was that it's now failing consistently at 14% instead of 13%. It's still failing with the timeout error from the JTAG server.
YuanLi_S_Intel
Regular Contributor
4 years ago
Hi,

It seems like we have a solution for this error message (Error(18939): Unexpected error in JTAG server: Timeout.):
https://www.intel.la/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2021/error-18939---unexpected-error-in-jtag-server--timeout-.html

Also, after that, can you change the TCK frequency to 6 MHz?
- leondietrich
  Occasional Contributor
  4 years ago
  Hi,
  
  thanks a lot for your help! We've fixed this issue now. One thing we'd like to share, for a potential future reader, is that in addition to the above mentioned article one needs to completely erase the flash prior to configuring. Our working solutions looks like the following:
  
  Power off the board. Waiting for the caps to be drained doesn't seam to be necessary.
  
  Set MSEL[2:0] to ON/OFF/OFF
  
  Power on the board.
  
  Erase the boards flash using the programmer tools
  
  Power off the board.
  
  Set MSEL[2:0] to OFF/OFF/OFF
  
  Power on the board
  
  Programm your *.sof file.
  
  It's also required to leave the JTAG chain in the default configuration while erasing the flash. Last but not least: If step 8 fails retry a couple of times until it stops failing (we usually don't need more than 3 tries). It also seams to be more reliable (programming fails less often) at 24MHz than 6MHz, which the programmer defaults to anyway.
Star
New Contributor
4 years ago
Hi,

Recently, I meet the same problem and struggle on it for couple of weeks. I read your solution and wanted to apply it to my PCB. But I encountered one problem when Erase the boards flash. I used the system console -->SDM Debugging Toolkit to erase the flash. However, the Toolkit replied message as shown below:

'QSPI Flash Sector 0x00000000: Erase Error'

It seems that the SDM Debugging Toolkit is useless when the device is not configured.

Can you clarify that how do you erase the boards flash using the programmer tools.

Thank you!
- leondietrich
  Occasional Contributor
  4 years ago
  Well,
  
  We're using the Quartus Programmer to erase the flash. Open the programmer from the Quartus menu -> click on "Auto Detect" to get the correct chain -> select erase for the flash chip -> press start
  - Star
    New Contributor
    4 years ago
    Hi,
    
    We've tried your method and the programming always fails at 99%. The error messages are shown below:
    
    'Unexpected error in JTAG server: JTAG chain broken
    
    Unexpected error in JTAG server: JTAG chain broken
    
    Unexpected error in JTAG server: JTAG chain broken
    
    Unexpected error in JTAG server: JTAG chain broken
    
    Device not responding
    
    Unexpected error in JTAG server: JTAG chain broken
    
    Operation failed'
    
    Have you ever met the same problem?

Forum Discussion

Intel Agilex F-Series dev kit cant be programmed by JTAG

26 Replies

Recent Discussions

MAX10 10M50 Development KIT Triple Speed Ethernet problem

About PCIe Daughter Cards for Agilex™ 3 FPGA and SoC C‑Series Development Kit

Stratix 10 FPGA Dev Kit VCCIO_FMC voltage issue

Stratix 10 Development Kit HiLo connector

Technical Assistance Request for Stratix® 10 SX SoC Development Kit (so#488775)