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leondietrich's avatar
leondietrich
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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Intel Agilex F-Series dev kit cant be programmed by JTAG

Hi, Im officially out of luck. After wasting an entire week on trying to get the programmer to work I posting my question within this forum. I've got multiple bit stream files I'd like to use for ...
  • leondietrich's avatar
    leondietrich
    5 years ago

    Hi,

    thanks a lot for your help! We've fixed this issue now. One thing we'd like to share, for a potential future reader, is that in addition to the above mentioned article one needs to completely erase the flash prior to configuring. Our working solutions looks like the following:

    1. Power off the board. Waiting for the caps to be drained doesn't seam to be necessary.
    2. Set MSEL[2:0] to ON/OFF/OFF
    3. Power on the board.
    4. Erase the boards flash using the programmer tools
    5. Power off the board.
    6. Set MSEL[2:0] to OFF/OFF/OFF
    7. Power on the board
    8. Programm your *.sof file.

    It's also required to leave the JTAG chain in the default configuration while erasing the flash. Last but not least: If step 8 fails retry a couple of times until it stops failing (we usually don't need more than 3 tries). It also seams to be more reliable (programming fails less often) at 24MHz than 6MHz, which the programmer defaults to anyway.

leondietrich's avatar
leondietrich
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I don't know if it's relevant but we're getting the following warning when trying to program said test-bitstream (which I've attached to this message for reference purposes):

Warning(19729): Current CMF data structure hash (0x15CD440C) is older version than latest CMF data structure but still allowable.
This might be transition period. You should update your CMF to latest version with hash { 0x8AC9CBBA } [ACDS 20.4 Release]

dsigner's avatar
dsigner
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5 years ago

I observe the Warning(19729) as well.

  • Mengjie's avatar
    Mengjie
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    5 years ago

    It should have something to do with Quartus compatibility issue from 19.x to 20.4, which means you probably fail to configure FPGA SOF 20.x again if FPGA has been configured with 19.x image right after power cycle. For devkit, it usually has an image in ASx4 flash for power-on boot-up, so if the AS programming file JIC file generated by 19.x, then it probably runs into FPGA 20.x SOF file configuration issue later on after power cycle. So there are two options to go, one is to erase ASx4 flash with Programmer, the other one is to set MSEL to JTAG only mode. BTW, please do use 19.x Programmer to configure 19.x SOF file, same to 20.x SOF file, otherwise, it may run into configuration issue as well.

    • dsigner's avatar
      dsigner
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      5 years ago

      I can confirm that setting SW1.1 to ON results in a successful load of the SOF after a power cycle.

    • Star's avatar
      Star
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      5 years ago

      It seems your analysis is reasonable. I wonder how to erase ASx4 flash with Programmer before the FPGA can be configured. Are there any documents illustrate this operation?