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leondietrich's avatar
leondietrich
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Intel Agilex F-Series dev kit cant be programmed by JTAG

Hi, Im officially out of luck. After wasting an entire week on trying to get the programmer to work I posting my question within this forum. I've got multiple bit stream files I'd like to use for ...
  • leondietrich's avatar
    leondietrich
    5 years ago

    Hi,

    thanks a lot for your help! We've fixed this issue now. One thing we'd like to share, for a potential future reader, is that in addition to the above mentioned article one needs to completely erase the flash prior to configuring. Our working solutions looks like the following:

    1. Power off the board. Waiting for the caps to be drained doesn't seam to be necessary.
    2. Set MSEL[2:0] to ON/OFF/OFF
    3. Power on the board.
    4. Erase the boards flash using the programmer tools
    5. Power off the board.
    6. Set MSEL[2:0] to OFF/OFF/OFF
    7. Power on the board
    8. Programm your *.sof file.

    It's also required to leave the JTAG chain in the default configuration while erasing the flash. Last but not least: If step 8 fails retry a couple of times until it stops failing (we usually don't need more than 3 tries). It also seams to be more reliable (programming fails less often) at 24MHz than 6MHz, which the programmer defaults to anyway.

dsigner's avatar
dsigner
Icon for New Contributor rankNew Contributor
5 years ago

I'm observing the exact same problem on two (out of two) boards.

Our boards are based upon the AGFB014R24A2E2VR0 device.

The result is the same with a very simple LED flashing design as with a design downloaded from:

https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/agilex/f-fpga/agilexfb_agfb014r24a2e2vr0_fpga_en_reva_v20.4b72_v1.0.zip

For example:
agilexfb_agfb014r24a2e2vr0_fpga_en_reva_v20.4b72_v1.0/examples/pcie_gen4/pcie_gen4_ep_ed.sof

Setting DEVICE_INITIALIZATION_CLOCK INIT_INTOSC does not change the result.

It fails at different TCK speeds, including 6MHz.

Running thousands of IDCODE cycles reports no problems.

Using an external USB Blaster (TerASIC) results in the exact same error messages.

I'm running Quartus Programmer Pro v20.4.0.72 under Ubuntu 18.4

I have no problems loading a sof on a CycloneV SoC board using the same host and SW.

All DIP switches settings are as when the boards were received and according to the default values in the user guide at:
https://www.intel.com/content/www/us/en/programmable/documentation/zbg1567202330317.html

I always get the error:

Error (18950): Device has stopped receiving configuration data
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18947): Device not responding
Error (209012): Operation failed

the first time after power cycle of the board. Then any subsequent programming operations results in:

Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18952): Error status: Synchronization failed
Error (209012): Operation failed