DDR2-SDRAM on Cyclone III DSP Kit (no NIOS)

I haven't used that particular board yet, but look at the example projects distributed with the development board - usually it is straight forward to glean how they use the pins relative to the IP Cores.

Are you intending to use the top and bottom banks of DDR as one wide interface or two independent ones?

Typically you can just duplicate the address lines for the top and bottom (if they have the same depth) but I don't know if you'll meet timing running the signals to both sides of the FPGA, but give it a try.

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...but look at the example projects distributed with the development board...

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There is none...

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Are you intending to use the top and bottom banks of DDR as one wide interface or two independent ones?

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I don't know. What would be better?

Now the problem is that local_ready (output) is low permanently after the first operation (read or write)... dropping the cl (http://alterauserforums.org/forum/showthread.php?t=3995) didn't help.

There is a reference project called cycloneIII_3c120_dev_niosII_standard in the installer. Found here: http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html

(http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html)

Yes, but I do not work with the NIOS. I use only the FPGA.

My question is specially about the DDR2 SDRAM Controller, how to use local_burstbegin and local_size. It doesn't get clear to me when reading the manual.

Those signals are described in this document: http://www.altera.com/literature/ug/ug_ddr_sdram.pdf

From the DDR docs, it seems as though those are avalon signals (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf - look for the section on burst transfers). You can interface to them directly, but why not drop your top level design file into SOPC builder and export the rest of the signals? The SOPC Builder will automagically take care of interfacing to burst enabled slaves even if your master is not.

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Those signals are described in this document: http://www.altera.com/literature/ug/ug_ddr_sdram.pdf

From the DDR docs, it seems as though those are avalon signals (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf - look for the section on burst transfers).

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I read that but my problem is that local_ready is deasserted after a few write cycles and I do not know why. Reading is no problem but if I write this problem occurs.

I have Quartus 9.0.

PLL Reference Clock = 100 MHz

Memory Clock = 125 MHz

Local Interface Clock = 62.5 MHz

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You can interface to them directly, but why not drop your top level design file into SOPC builder and export the rest of the signals? The SOPC Builder will automagically take care of interfacing to burst enabled slaves even if your master is not.

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How does that work? I am a beginner in Quartus...

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...local_ready is deasserted after a few write cycles and I do not know why. Reading is no problem but if I write this problem occurs.

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Can you post a screen shot of the simulation including all the memory port signals?

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How does that work?

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If you mean ... How do you do it, then ... I am assuming you have an HDL design and are attempting to hook up the DDR2 Controller (found in SOPC Builder) - stop me if I'm wrong. You can create a custom component for the HDL entity (top level or not) in SOPC Builder that is attempting to control the DDR. From within SOPC Builder, click File -> New Component. Read the intro, then click the other tabs adding files, specify the top level component, and set which ports compose your component's avalon interface and which should be exported as signals outside of SOPC Builder (ie. to connect to pins or other none SOPC components).

If you mean ... What magic does it perform, then ... this is an interesting read http://www.altera.com/literature/hb/qts/qts_qii54003.pdf. Skip to the section on "Burst Adapters." But basically, the SOPC Builder inserts a state machine to take care of it.

Hey immutableman, thanks for your help! :)

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Can you post a screen shot of the simulation including all the memory port signals?

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Well, I didn't do any simulation.

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If you mean ... How do you do it, then ... I am assuming you have an HDL design...

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I have a block design file and there I use some blocks which I created with VHDL. And I just want to read from and write to the DDR2-SDRAM using this Megafunction called "ddr2-sdram high performance controller".

Glad to be of help.

Okay, how is the DDR core configured? Is it set to Native or Avalon? I'll assume native, in which case the ddr docs say that you have to assert local_wdata_req after the write command has been accepted (see page 3-20 through 21), also set local_size = 1. Can you try this if you haven't and post a signal tap with ALL the signals found in figure 3-13 of the DDR controller docs I linked to above (or at very least all of the local side of the core)?