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local_ready is deasserted after a few write cycles and I do not know why. Reading is no problem but if I write this problem occurs.
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Can you post a screen shot of the simulation including all the memory port signals?
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How does that work?
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If you mean ... How do you do it, then ... I am assuming you have an HDL design and are attempting to hook up the DDR2 Controller (found in SOPC Builder) - stop me if I'm wrong. You can create a custom component for the HDL entity (top level or not) in SOPC Builder that is attempting to control the DDR. From within SOPC Builder, click File -> New Component. Read the intro, then click the other tabs adding files, specify the top level component, and set which ports compose your component's avalon interface and which should be exported as signals outside of SOPC Builder (ie. to connect to pins or other none SOPC components).
If you mean ... What magic does it perform, then ... this is an interesting read
http://www.altera.com/literature/hb/qts/qts_qii54003.pdf. Skip to the section on "Burst Adapters." But basically, the SOPC Builder inserts a state machine to take care of it.
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