Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

DDR2-SDRAM on Cyclone III DSP Kit (no NIOS)

Hi, I am using the dsp development kit, cyclone iii edition (http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html). I wanted to use the DDR2-SDRAM but unfortunately there is no ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Those signals are described in this document: http://www.altera.com/literature/ug/ug_ddr_sdram.pdf

From the DDR docs, it seems as though those are avalon signals (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf - look for the section on burst transfers). You can interface to them directly, but why not drop your top level design file into SOPC builder and export the rest of the signals? The SOPC Builder will automagically take care of interfacing to burst enabled slaves even if your master is not.