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Those signals are described in this document:
http://www.altera.com/literature/ug/ug_ddr_sdram.pdf From the DDR docs, it seems as though those are avalon signals (
http://www.altera.com/literature/manual/mnl_avalon_spec.pdf - look for the section on burst transfers).
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I read that but my problem is that
local_ready is deasserted after a few write cycles and I do not know why. Reading is no problem but if I write this problem occurs.
I have Quartus 9.0.
PLL Reference Clock = 100 MHz
Memory Clock = 125 MHz
Local Interface Clock = 62.5 MHz
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You can interface to them directly, but why not drop your top level design file into SOPC builder and export the rest of the signals? The SOPC Builder will automagically take care of interfacing to burst enabled slaves even if your master is not.
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How does that work? I am a beginner in Quartus...
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