DDR2-SDRAM on Cyclone III DSP Kit (no NIOS)

Glad to be of help.

Okay, how is the DDR core configured? Is it set to Native or Avalon? I'll assume native, in which case the ddr docs say that you have to assert local_wdata_req after the write command has been accepted (see page 3-20 through 21), also set local_size = 1. Can you try this if you haven't and post a signal tap with ALL the signals found in figure 3-13 of the DDR controller docs I linked to above (or at very least all of the local side of the core)?