Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI haven't used that particular board yet, but look at the example projects distributed with the development board - usually it is straight forward to glean how they use the pins relative to the IP Cores.
Are you intending to use the top and bottom banks of DDR as one wide interface or two independent ones? Typically you can just duplicate the address lines for the top and bottom (if they have the same depth) but I don't know if you'll meet timing running the signals to both sides of the FPGA, but give it a try.