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LVDS pin detail on Arria 10
Hi, I am using Arria 10 FPGA in one of our project. OPN: 10AX066N2F40E1HG. I see that Bank 3D is dedicated to LVDS ( picture below from HW schematic). But, my FPGA pin planner says the pin is 1.8 V(default). there is a drop down option to choose LVDS, but it was never chosen. the pin was left at 1.8V, and bit file was generated and it works fine in Hardware. I have two questions regarding this. 1) Is the fpga pin planner setting ignored and the pins are treated as differential LVDS? 2) Can the LVDS pin be used as single ended instead of differential? ThanksSignal Tap Rapid Recompile
Hi all, I am using quartus 18.1 Standard edition. I have enabled signal tap in my design. I added few signals to the signal tap, and also changed the trigger. I understand that I need to recompile to get the updated signal tap into my design. But, here is my following question. I see that there is a rapid recompile message in the signal tap window, as shown below in the picture. But once I go to processing tab to start rapid recompile, I see that the option is greyed out as shown below. How do I start rapid recompile in quartus 18.1? any tricks that I am missing? Thank you.Unused Transceivers in Arria 10
Hi, I am using quartus 18.1 Standard edition. FPGA : Arria 10 : 10AX066N2F40E1HG I was advised to use the following setting in QSF to protect the unused transceivers from degrading. set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON How can unused transceivers degrade? Regards, ManojProgramming sof into FPGA from command line
Hello, I have an intel FPGA devkit with Arria10. I am able to program the FPGA Sof through the quartus programmer GUI. But, when I try to use the command line option, then i get the Error (213013): Programming hardware cable not detected. Here is the output of my jtagconfig --debug my devkit is in index 2 and I tried the following command with no luck. quartus_pgm -c 2 -m jtag -o "p;test.sof@1" can you help?Re: Programming non volatile memory of FPGA Devkit - Intel Arria 10 soc devkit
Hi, I was able to program .jic using active serial mode. SW5 ( MSEL (2:0)) = 010 for Active Serial Fast mode SW4.2 = ON to disable Max V from the JTAG chain SW6.4 = OFF to load user image from flash. couldn't figure out .pof solution yet. but this ticket can be closed now. thanksRe: Flash memory not detected - Arria 10 Development kit
Hello FvM, Thanks for your response. Yes I did try to follow the steps mentioned in the user guide and the switch configuration mentioned there. There are couple of updates and questions from my end. 1) There was an option to add flash manually in the programmer, by clicking on the cpld (5M2210Z). I was able to add the CFI flash and it is showing up in the tool. image below. Is this also a correct way to add the flash? 2) Let's say I would like to go with pof option using the above step, will it still be fine? If yes, then which mode should I use to generate the pof?. where should I find that information? 3) Once I generate the pof with correct mode and configuration, should I program the CFI flash and then also the pag_0 and option_bits as shown below? thanks for your time.
