User Profile
MK_ABQ
ContributorJoined 4 years ago
User Widgets
Contributions
Re: LVDS Output of FPGA
Hi AqidAyman_Altera , I see an option to tweak I/O delay. This will be very useful for me. my FPGA OPN is 10AX066N2F40E1HG. I am trying to find which setting from the following table applies to my FPGA, and it's confusing. Does my FPGA LVDS serdes I/O belong to slow model (E1H) highlighted part? or Fast Model Extended?LVDS Output of FPGA
Hi all, I am using Arria 10 FPGA part number: 10AX066N2F40E1HG for one of my projects. There is a clock output from FPGA that goes to an external chip. This clock is configured as LVDS. Currently debugging an issue, and focused on enhancing the signal quality at the output of the FPGA. The output signal we measure in scope is not as good as we would expect. We expect a step signal, but the testing output shows a triangular signal! I have the following questions. 1) Is there settings/knobs I could tweak in my LVDS IP, or any other ideas to improve output signal quality? ( I learned about pre_emphasis setting), But other ideas could help. 2) Is there an inbuilt tool within FPGA to check the eye diagram or measure the output signal quality?instead of relying on an oscilloscope?. Note: I am using Quartus 2018 standard version. Let me know if you need further information. Thankyou.LVDS pin detail on Arria 10
Hi, I am using Arria 10 FPGA in one of our project. OPN: 10AX066N2F40E1HG. I see that Bank 3D is dedicated to LVDS ( picture below from HW schematic). But, my FPGA pin planner says the pin is 1.8 V(default). there is a drop down option to choose LVDS, but it was never chosen. the pin was left at 1.8V, and bit file was generated and it works fine in Hardware. I have two questions regarding this. 1) Is the fpga pin planner setting ignored and the pins are treated as differential LVDS? 2) Can the LVDS pin be used as single ended instead of differential? ThanksSignal Tap Rapid Recompile
Hi all, I am using quartus 18.1 Standard edition. I have enabled signal tap in my design. I added few signals to the signal tap, and also changed the trigger. I understand that I need to recompile to get the updated signal tap into my design. But, here is my following question. I see that there is a rapid recompile message in the signal tap window, as shown below in the picture. But once I go to processing tab to start rapid recompile, I see that the option is greyed out as shown below. How do I start rapid recompile in quartus 18.1? any tricks that I am missing? Thank you.Unused Transceivers in Arria 10
Hi, I am using quartus 18.1 Standard edition. FPGA : Arria 10 : 10AX066N2F40E1HG I was advised to use the following setting in QSF to protect the unused transceivers from degrading. set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON How can unused transceivers degrade? Regards, ManojProgramming sof into FPGA from command line
Hello, I have an intel FPGA devkit with Arria10. I am able to program the FPGA Sof through the quartus programmer GUI. But, when I try to use the command line option, then i get the Error (213013): Programming hardware cable not detected. Here is the output of my jtagconfig --debug my devkit is in index 2 and I tried the following command with no luck. quartus_pgm -c 2 -m jtag -o "p;test.sof@1" can you help?
