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PLL Reconfiguration using mif for strarix 10
Hi ) I want to generate PLL with mif setting for 5 clock speed. for example, input clock is 100MHz, I want to generate PLL which have 2 output clks. but it should be reconfigurable with mif files. Output clock used 30,40,50,60,60 Mhz 2) with 2 options, 1 mif file is generated for 30 Mhz and 40 Mhz. with this , MIF can be updated. This is OK , but for the RTL simulation how to change from 20 Mhz to 60Mhz ? if 60Mhz option start 48 = 30 (hax) I put address = 0 ( mig option is [9:8] = 0 ) and mgmt_writedata = 30(hex ) mgmt_write than waitrequest is 0 --> 1 and again 1-->0 but output clock is what I wanted. Can u tell me how to do reconfiguration PLL speed using mif ?Re: How to generate reconfig for S10 ?
other about from ALTPLL to IOPLL intel FPGA IP. this one from ATL_RECONFIG to IOPLL Reconfig Intel FPGA IP. Re-generation ok, but I will don't know how to . There are too many port changed and pll_scanclk, pll_scanclkena, pll_scandata, pll_scandataout, pll_scandone, can't see in 21.x also old one doesn't require *.mif but in21.x is required . My old project can synthesis without error , it means that I was not need *.mif 1) *.mif how to make for replacement of old ip from 13.x 2) port missing so many port are not shown in 21.x. how to generate in 21.x , Let me get right way thanksHow to generate reconfig for S10 ?
HI, This reconfig from ver 13.x now I want to generate at 21.x which has like this module reconfig_pll_pllrcfg_vvr ( busy, clock, counter_param, counter_type, data_in, data_out, pll_areset, pll_areset_in, pll_configupdate, pll_scanclk, pll_scanclkena, pll_scandata, pll_scandataout, pll_scandone, read_param, but generated from quartus pro 21.x I can't find PLL which has scanclk / scnaldata, Can you tell me how to generate ?How to generate ALLPLL in S10 ?
Hi, I am tried to converter old pll in quartus 13.1 to quartus pro 21.x OLD ALLPLT has scanclk/scandataout port from tool . // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module pll_cnfgrbl ( areset, configupdate, inclk0, scanclk, scanclkena, scandata, c0, c1, c2, locked, scandataout, scandone); input arese how to generate same PLL for s10 ? I can't see scanclk/scankena/scnadata pin option in quartus pro 21.xRe: USing VCS RTL Simulation from quartus pro generated code
HI, I thinks that we are not same page. Can you see attachment from Quartus pro Just generated one PLL which name is test. In there, there are script for vcs_mx. 1) Script said source ~~~~~~/vcsmx_setup.sh --> NOT WORKING ( My problem to run simulation) 2) The template is not said as Intel Quartus Prime Pro Edition User Guide: Third-party Simulation Even same Quartus prime pro version as doc, Why generated script file contents is not same? Would check it again? ThanksRe: USing VCS RTL Simulation from quartus pro generated code
\ ->Generated simulation Model. 2) Actually, In mentor it is easy A) After generation IP from quartus pro, turn off it B) just want to run the simple script. ( eaxmple.run) vlogen /!~~~path /generated_IP_name.v ------------------------------------------- ----MISSING PART (wanted part ) ---------------- ------------------------------------------- vcs top_name -kdb simv c) >> example.run How to do it ? d) ur example is for using Quartus, even image link is broken ThanksRe: USing VCS RTL Simulation from quartus pro generated code
HI , this is my answer Have you Generate the Simulator Setup Script in the document section 2.5.3.2.1. ? --> YES SEE second screen shots 1) scripts result are not same as Intel Quartus Prime Pro Edition User Guide: Third-party Simulation 2) Without ignore comments in script, cmd> source vcs_setup.sh should be working. but not. 3) Can I get simple example such as only 1 PLL design for VCS RTL simulation . to see waveform ( generated FSDB ) Thanks
