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minjoolee's avatar
minjoolee
Icon for New Contributor rankNew Contributor
4 years ago

How to generate reconfig for S10 ?

HI,

This reconfig from ver 13.x

now I want to generate at 21.x

which has like this

module reconfig_pll_pllrcfg_vvr
(
busy,
clock,
counter_param,
counter_type,
data_in,
data_out,
pll_areset,
pll_areset_in,
pll_configupdate,
pll_scanclk,
pll_scanclkena,
pll_scandata,
pll_scandataout,
pll_scandone,
read_param,

but generated from quartus pro 21.x

I can't find PLL which has scanclk / scnaldata,

Can you tell me how to generate ?

2 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    You shouldn't double-post. See my reply in the other forum.

  • minjoolee's avatar
    minjoolee
    Icon for New Contributor rankNew Contributor
    4 years ago

    other about from ALTPLL to IOPLL intel FPGA IP.

    this one from ATL_RECONFIG to IOPLL Reconfig Intel FPGA IP.

    Re-generation ok, but I will don't know how to .

    There are too many port changed and

    pll_scanclk,
    pll_scanclkena,
    pll_scandata,
    pll_scandataout,
    pll_scandone,

    can't see in 21.x

    also old one doesn't require *.mif but in21.x is required .

    My old project can synthesis without error , it means that I was not need *.mif

    1) *.mif

    how to make for replacement of old ip from 13.x

    2) port missing

    so many port are not shown in 21.x. how to generate in 21.x ,

    Let me get right way

    thanks