How to generate reconfig for S10 ?

other about from ALTPLL to IOPLL intel FPGA IP.

this one from ATL_RECONFIG to IOPLL Reconfig Intel FPGA IP.

Re-generation ok, but I will don't know how to .

There are too many port changed and

pll_scanclk,
pll_scanclkena,
pll_scandata,
pll_scandataout,
pll_scandone,

can't see in 21.x

also old one doesn't require *.mif but in21.x is required .

My old project can synthesis without error , it means that I was not need *.mif

1) *.mif

how to make for replacement of old ip from 13.x

2) port missing

so many port are not shown in 21.x. how to generate in 21.x ,

Let me get right way

thanks