minjoolee
New Contributor
New ContributorPLL Reconfiguration using mif for strarix 10
Hi )
I want to generate PLL with mif setting for 5 clock speed.
for example, input clock is 100MHz, I want to generate PLL which have 2 output clks.
but it should be reconfigurable with mif files.
Output clock used 30,40,50,60,60 Mhz
2)
with 2 options, 1 mif file is generated for 30 Mhz and 40 Mhz.
with this , MIF can be updated.
This is OK , but for the RTL simulation how to change from 20 Mhz to 60Mhz ?
if 60Mhz option start 48 = 30 (hax)
I put address = 0 ( mig option is [9:8] = 0 )
and mgmt_writedata = 30(hex )
mgmt_write
than waitrequest is 0 --> 1 and again 1-->0
but output clock is what I wanted.
Can u tell me how to do reconfiguration PLL speed using mif ?
