[IP_Compiler for PCIe__Cyclone IV GX] How to use the testbenches example, not the chaining_DMA one
Hi Everyone, I want to use the IP Block IP_Compiler for PCIe, for a FPGA Cyclone 4 GX. Firstly, I want to test that IP block via the automatically generated testbenches. I installed Quartus Prime 18.1.0.625 Edition lite (the free one). I generated the IP block via the Megawizard. Examples were automatically generated: chaining_DMA and the other examples that are interesting me. How to use these other examples? The User guide only explains the content on these blocks but not how o use them. That document is available here: https://docs.altera.com/v/u/docs/655049/ip-compiler-for-pci-express-user-guide Thank you in advance for your assistance[IP_Compiler for PCIe__Cyclone IV GX] How to start the chaining_dma example
Hi everyone, I want to use the IP Block IP_Compiler for PCIe, for a FPGA Cyclone 4 GX. Firstly, I want to test that IP block via the automatically generated example chaining_DMA. I installed Quartus Prime 18.1.0.625 Edition lite (the free one). I generated the IP block via the Megawizard. I installed and opened Modelsim starter edition 2020.1. I followed the indication in the starter guide, section 2-12 (page 28 / 372). But after typing the command runtb.do, I got the error "Error loading design" that blocked the simulation. Compilation happened successfully with 25 warnings, minor I think : (vcom-1236) Shared variables must be of a protected type. Has anyone an idea on what to do? Who successfully reached the output of Example 2-1 of the User guide by following the indications of that User guide? That document is available here: https://docs.altera.com/v/u/docs/655049/ip-compiler-for-pci-express-user-guide Thank you in advance for your assistance
Quartus 26.1.1: GTS AXI Streaming PCIe Reset Output Connection Error
Hi everyone, After upgrading from Quartus Prime Pro 25.1.1 to 26.1.1, I encountered a new connectivity error in Platform Designer related to the GTS AXI Streaming IP for PCI Express. The design was working correctly in version 25.1.1. However, after the upgrade, Platform Designer reports the following error: intel_pcie_gts_0.p0_pin_perst_n must be connected to a reset source According to the Altera documentation, p0_pin_perst_n is an asynchronous reset output derived from the PCIe Hard IP's PERST# input. Platform Designer also identifies this interface as a "Reset Output", so it seems inconsistent that the tool requires it to be connected to a reset source. My questions: Is this a known issue or regression in Quartus Prime Pro 26.1.1? Has the handling of p0_pin_perst_n changed between versions 25.1.1 and 26.1.1? Is there a recommended workaround, such as exporting the unused reset output, or is an additional connection now required? I would appreciate any clarification or suggestions. Thanks in advance!
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[PCIE_DESIGN_EXAMPLE][AGILEX7][QUARTUS25.3.0] - failed at elaboration process
Hello, I am trying to simulate with questa fe the pcie design example (with pipe mode for external dma controller) based on agilex7 generated with quartus pro 25.3.0 but i am facing these issues when i run this script under "pcie_ed_sim_tb/pcie_ed_sim_tb/sim/mentor" as follow : vsim -do run_msim.tcl # ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x16_l0) is not on a downward path. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x16_l0' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x16_l0. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x4_l12) is not on a downward path. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x4_l12' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x4_l12. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x4_l4) is not on a downward path. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x4_l4' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x4_l4. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x8_l8) is not on a downward path. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x8_l8' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x8_l8. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Warning: (vsim-3008) [CNNODP] - Component name (i_rxpipe0__dirfeedback) is not on a downward path. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Error: (vsim-3043) Unresolved reference to 'i_rxpipe0__dirfeedback' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_rxpipe0__dirfeedback. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Warning: (vsim-3008) [CNNODP] - Component name (i_rxpipe0__linkevaluationfeedbackfiguremerit) is not on a downward path. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 # ** Error: (vsim-3043) Unresolved reference to 'i_rxpipe0__linkevaluationfeedbackfiguremerit' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_rxpipe0__linkevaluationfeedbackfiguremerit. # Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589 ..... I also have followed the Altera recommendations : Note: Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3, you are required to add "-suppress 2732" to USER_DEFINED_COMPILE_OPTIONS and "-suppress 10000 " to USER_DEFINED_ELAB_OPTIONS in the run_msim.tcl simulation script manually for a successful simulation with the Questa simulator. But i am still facing these above issues. What can i do ? Regards, Frederic
R-TILE PIPE DIRECT MODE SIMULATION PHY STATUS ISSUE IN RESET RELEASE SEQUENCE
HI, I am currently working on r-tile pipe direct mode simulation in questasim. So, initially i have generated r-tile ip with configuration of pipe direct mode, 16x1. I have generated hdls using generate hdl option(enabling verilog,questasim). I have written pipe control fsm to provide control inputs to r-tile ip. Ref_clock1,ref_clock2 frequency is 100mhz. Reconfig_clock frequency is 100mhz. pipe_direct_pld_tx_clk_out_o from ip is 500mhz(validated in sim) So, i start with providing ninit_done using reset release ip. once nint_done goes low, i am providing pin_perst_n to high. then pin_perst_n_o goes high. After sometime, pipe_direct_pld_tx_clk_out_o becomes active. So, i am waiting for ln0_pipe_direct_tx_transfer_en_o to goes high. once this signal goes high, i will release ln0_pipe_direct_pld_pcs_rst_n_i to high. I am checking the phy signal to toggle. but from beginning itself it stays low, it never toggles. Along with this standard procedure, i tried 2 more possibilities i tried, After i released the ln0_pipe_direct_pld_pcs_rst_n_i to high. I provided the ln0_pipe_direct_txdetectrx_i to high. No response from phy_status. After i released the ln0_pipe_direct_pld_pcs_rst_n_i to high. I provided the ln0_pipe_direct_txdetectrx_i , rx_standby to high. still No response from phy_status I am attaching some screenshots of waveforms. Kinly look into it and help me out. I am really stuck at midway..Terasic P16E-FMCP PCIE Express 3.0 compatibility issues with AMD processors
Hi I bought the Terasic P16E-FMCP to use on my Terasic Apollo S10 SOM board for PCI Express 3.0 implimentation. However after testing the included program, it did not work, so I emailed Terasic Support and they told me it was only tested on Intel CPU and it appears never tested on AMD. So they made me run a simple program called System Information Viewer from rh-software.com which tested the information sent and received from the PCI endpoint and it appears there are errors stimming back from the demo program does not natively run on AMD processors. So for the past 6 months, Terasic has been dragging there feet on this issue, telling me they will work on a solution but I must go out and purchase another computer by Intel, then run several versions of Quartus Pro, starting from 19.1, through 23.3, I must download them individually. I told them I am not doing this, I am not being paid to test out your code, I simply purchased the board direct from you for $650, and NOWHERE on the website does it publish it works only with Intel CPU. Instead they are pointing the fingers at me saying I'm delayin a resolution on this issue by not testing out there code, I told them that IS YOUR JOB! I AM NOT EMPLOYED BY TERASIC! Terasic is a partner program of Intel, they have all the means to reach out and contract a device driver writer and solve this incompatiblity issue. This is beyond my expertise. They simply won't do it. Does anyone have a solution to this problem? Why are they passing the buck at me?
PCIe stuck at reset Agilex5
Hi Altera Team, I'm trying to get PCIe connection working on our custom board. We had some problems with our design. Reset pin (CF128) is connected to CF121 on board (we forgot to connect it). At the start i set CF121 to '1', to get PCIe out of reset. When fpga boots, all clocks should be up and stable. Based on "Link Training Debugging Flow" my IP core is in reset and i should check pin_perst_n. Pin is set to '1', but IP is still in reset? What could be the couse? Is there a chance for this behaviour if core can't detect root? Do i need IO_Pll to lock for core to get out of reset? I use example design for PCIe, with different pinout. Device: A5ED065BB32AE6S - Common clock architecture
