Arria® 10 FPGA PCIe 3.0 Endpoint is not compatible with PCIe 4.0 capable system.
This is an issue sharing: When inserted Arria 10 PCIe Gen3 design endpoint card into a Gen4 capable Host/CPU, the PCIe link might keep cycling between L0->Recovery.Rcvlock->Recovery.Rcvconfig->Recovery.Idle->L0->Recovery.Rcvlock..... Description: Data Link Feature Exchange is not part of PCIe Gen3.0 specification, and it is an optional feature per PCIe Gen4.0 Specification. The Intel® Arria® 10 FPGA PCIe 3.0 IP core will treat 4.0 Data Link Features Exchange as unsupported DLLP type (as per the PCIe 3.0 spec), unsupported DLLP type is not being flagged as valid DLLP, so does not ungate the InitFC. When this happens, no error is reported by the Intel® Arria® 10 FPGA. This is an expected behaviour. Resolution: To work around this problem, disable the Data Link Feature Exchange in PCIe 4.0 system BIOS [Base spec 4.0 chapter 7.7.4.2 Data Link Feature Capabilities Register (Offset 04h)] to be compatible with legacy hardware.
Need PCI Express 5.0 for your next FPGA design? Check out Intel® Agilex™ I-series and M-series FPGAs
Are you designing systems that need PCI Express (PCIe) 5.0 capability? If so, you’ll want to take a good look at the Intel® Agilex™ I- and M-series FPGAs and SoC FPGAs because these programmable-logic devices incorporate PCIe 5.0 capabilities and have just passed PCI-SIG compliance tests.
FPGA writing to SSD
FPGA A (which is part of an existing system) transmits data using Serial Lite at 24 Gb/s. This data shall be received by FPGA B (to be designed) and written to an external storage device (SSD or multiple SSDs). The data volume is in the order of < 10 Terabytes. I thought of 2 possible approaches: 1. Connect the storage devices directly to FPGA B (using a custom board) and have the FPGA write directly to them. (I assume this will require implementing an NVMe controller in FPGA B). 2. Install FPGA B inside a PC like system where it will communicate via PCIe and do DMA transactions towards the storage devices. Which of the above approaches offers better performance ?
