Agilex 5 with HPS Cryptographic services and bootflow
Hi I have a question regarding boot flow on agilex 5 with HPS with security in mind. I am aware how this is typically implemented on other SoCs like NXP but as for the Agilex - I just started working on this SoC From what I understand (based on the docs and tf-a source code in particular VAB part) the flow is the following: SDM verfies fsbl signature and loads it SDM releses HPS from reset Fsbl loads next stages (BL31 BL33) each time communicating with SDM through mailbox asking SDM to verify the image signaturure Then we can be sure that we only use legitimate binaries. Am I right? I have found in the agilex 5 product table that some variants are equipped with Cryptographic services and some not. Are these Cryptographic services needed to perform the above flow? If the variant I have is not equipped with such IP is there any other way to securely boot all boot chain up to Linux?Agilex 5 with HPS
Hi, I have a question regarding Agilex 5 with HPS. I intend to deliver to the client a device based on Agilex 5 and HPS, but initially the HPS must remain fully offline. In other words, once the device is shipped, I need to ensure with 100% certainty that no software or program can be executed on the HPS, and that there is no possible way for the client to interact with or enable it prematurely. At the same time, I need to retain the ability to remotely deploy a new FPGA bitstream at a later stage, which will enable the HPS once the HPS software development is completed. Is such a workflow achievable on this platform?
25.3 PRO Release
Version: Release 25.3 PRO Quartus Build/TAG: B109/QPDS25.3_REL_GSRD_PR Release Date: October 10, 2025 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10, Arria® 10 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2025.10/ Major Features Released Support of GHRD 2.0 in Agilex™ 5 which includes foundational boot to Linux, ability to create compatible phase 2 bitstreams, parameterized HPS for maximum performance and best practices. Support of GSRD 2.0 Yocto layers for the Agilex 5 E-Series Premium DevKit with OOBE daughtercard for the GHRD 2.0 baseline design. Agilex 5 GSRD Development User Experience Improvement through KAS using a graphical/text interface to configure a limited number of high-level options on top of simplified Yocto recipes. - GSRD 2.0 with Kas Build System Support for running Agilex 5 Simics Simulation under the GSRD 2.0 framework. Booting from SD Card and QSPI is supported. - Exercising Simics Simulation from GSRD 2.0 Support GHRD and GSRD for Agilex™ M-Series PRQ HBM2e for DK-Sl-AGM039EA development kit. The GSRD is capable of booting to Linux. - Build the GSRD for DK-DEV-AGM039EA Hypervisor Multi-OS Support Example, demonstrating Linux and Zephyr running side-by-side in the HPS cluster. - HPS Xen Hypervisor GSRD System Example Design: Agilex™ 3 FPGA and SoC C-Series Development Kit Support for monitoring of SEU errors from the SDM in the HPS in Agilex™ 7. Add capability to measure the latency of Linux SMC calls. Support Nios V Lockstep application with a fail-safe mechanism
Qsys: EMIF IP Core: usr_reset associated Clock
Hello, I am a bit confused by the Usage of the emif_usr_reset_n signal of the Intel EMIF IP Core. I have added a EMIF IP Core to our Platform Designer project. Based on the Documentation (4.1.1.14. emif_usr_reset_n for DDR3) I would assume the usr_reset output to have an associated clock (emif_usr_clk) with a synchronous deassertion: However in Platform Designer this reset appears without any associated clock and I get reset adapters when assigning it to reset inputs which require synchronous deassertion. I tried to explicitly set the emif_usr_reset_n output associated clock and synchronous edge, by applying this setting: But then I end up with the following Warning and I can also confirm, that the corresponding emif.ip file does not have the expected associated clock setting. So my question is: Is the documentation (4.1.1.14. emif_usr_reset_n for DDR3) correct and is the emif_usr_reset_n output really synchronous deasserted? Why does Platform Designer does not recognize the correct clock association for this signal? How do I configure the IP in a correct way to avoid any unnecessary or unexpected automatically inserted reset adapter? best regards Fabianmmc blocks written = error
Hi, By using Agilex-i series dev kit.I'm able to write a OS file from memory[0] region of ddr to mmc,but unable to write a file from memory[1] region of ddr to mmc. bdinfo log lmb_dump_all: memory.cnt = 0x2 / max = 0x10 memory[0] [0x0-0x7fffffff], 0x80000000 bytes flags: 0 ( 2GB ) memory[1] [0x280000000-0x3ffffffff], 0x180000000 bytes flags: 0 ( 6GB ) While tranfering a OS file from memory[1] region of ddr to mmc. Error pop up message as " mmc blocks written = error ". Thanks M Gokulraj
Cyclone 5 FPGA UART driver, and read/write functions.
I am using a Cyclone 5 MitySOM on the Critical link dev kit. I am trying to setup a custom UART (RX, TX) lines from the FPGA GPIOs, not going through any external chip other than and FTDI connected to a PC. I prefer to have this code in System Verilog. I have found some example of source for the RX and TX transactions, but nothing on how they get integrated into the FGPA system. Can you please provide me some detail, example code, etc. of how I can setup a custom UART (115200), that I can send Hello World to the PC and have it come out in a terminal window. Want to use this for log/debugging as well as a simple menu system to process incoming commands to perform actions real time. Thanks, Chris
Case (Z2-126625)|1002715
Hello, We request your help to provide us with FMD, TSCA and PFAS for below PNs: BX8071512500 BX8071512700 BX8071513500 BX8071513700 CM8066201920404 SR2L6 CM8071504555019 CM8071504820805 I210T1 I210T1BLK And we need you to confirm if part below part is correct and provide a data sheet for it IC PRE-PROG JSD100 EPM240T100I5N, EPM240T100C5N Please keep the following case number in all your replies. Case (Z2-126625)|1002715
