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Gokulraj's avatar
Gokulraj
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9 months ago

mmc blocks written = error

Hi,

By using Agilex-i series dev kit.I'm able to write a OS file from memory[0] region of ddr to mmc,but unable to write a file from memory[1] region of ddr to mmc.

bdinfo log

lmb_dump_all:
memory.cnt = 0x2 / max = 0x10
memory[0] [0x0-0x7fffffff], 0x80000000 bytes flags: 0 ( 2GB )
memory[1] [0x280000000-0x3ffffffff], 0x180000000 bytes flags: 0 ( 6GB )

While tranfering a OS file from memory[1] region of ddr to mmc. Error pop up message as " mmc blocks written = error ".

Thanks

M Gokulraj

Arm Processor
Hps Arch
Sw Development

6 Replies

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    9 months ago

    Hi Gokulraj,

    Thanks for using Altera Forums, I'm Kian and will be looking into this case. Let me check on this issue and revert to you later.

    Thanks

    Regards

    Kian

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    9 months ago

    Hi Gokulraj,

    Sorry for the delay in getting back, was checking with our factory apps on this.

    Apparently this is a known issue as there is another case with similar issue, quote from the other case findings

    1. MMU table missing the mapping for higher memory bank, and the issue only being seen with dcache turn on, as this would trigger MMU run, and when MPU access those memory region not defined in MMU table mapping would causing system hang
    2. With logical block enable, the default logic memory layout would set reserve to higher memory region, hence any feature like sf, tftp and wget which calling lmb check would prevent MPU to access higher memory region

    I've attached the Patches.zip file here but it is based on the latest build thus might not be compatible if you're running an older version of the code.

    You can try to manually edit the files indicated here (add in those in green) and rebuild uboot fsbl and itb (or you can refer to the patches on the changes)

    Thanks

    Regards

    Kian

    • Gokulraj's avatar
      Gokulraj
      Icon for New Contributor rankNew Contributor
      9 months ago

      Hi Kian,

      It's very hard to identify what is done in the attached image.Please attach the clear image ASAP.

      In the meantime i'll check with patches.

      Thanks

      Gokul raj

    • Gokulraj's avatar
      Gokulraj
      Icon for New Contributor rankNew Contributor
      9 months ago

      Hi kian,

      I've checked with the patches still the issue not resolved and please confirm me do you transferred any OS file from the ddr(memory[1]) region to mmc.

      Check with the attached image for error log and i have configured load address as 0x280000000.

      Thanks

      Gokul raj

    • Gokulraj's avatar
      Gokulraj
      Icon for New Contributor rankNew Contributor
      9 months ago

      Hi,

      Here the main issue is in reading 64bit memory address.

      "mmc write" command can take 32bit memory address and its is working fine,but while using 64bit memory address it's locked in timeout error. I've confirmed it by debugging the u-boot code while using "mmc write" command.

      will you check with the files related to mmc in driver and include folder in your side and give me a solution.

      Thanks

      Gokul raj

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    8 months ago

    Hi,

    Apologies for the delay reply as I saw that there is already a duplicate thread on the same issue

    https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/How-to-access-the-8GB-ram-of-DDR-in-Agilex-7/td-p/1660123/page/2

    Been discussing with my colleague on the cases and he mentioned that we will use the other thread to follow up. May I know whether can set this thread to community support and we will use the other thread to continue on the debugging.

    Thanks

    Regards

    Kian