USB-Blaster not detected by Quartus 23.1
Hi, 1 - install quartus prime lite 23.1 - OK 2 - install USB-blaster driver - OK (apear Altera USB-Blaster working properly on device manager) But, when I click "Tools->Programmer->Hardware Setup-> Current selected hardware" the usb-blaster don't apear to be selected (but it's ok on device manager). I've done this sequence using Windows 11 22H2 and Windows 10 22H2, and I have the same problem. Whai is missing/ problem? Thank you.
Quartus-Questa Compilation Simulation Dependency Management
Hello, I had a question about dependency management using Quartus and Questa. For a FPGA project that I'm working on, I noticed that when I do Tools->Run Simulation->RTL Simulation, a .do file gets generated, with vlog commands with the systemverilog/library/package files that need to get compiled. However, when trying to use it to run vsim commands in Questa, I noticed that some files were failing to include each other, and when going through the .do file, I noticed that some dependencies were not properly resolved (eg. a package would be compiled after the systemverilog file that tries to import it). For other softwares, I'm aware of functions such as smartorder for Xcelium and autoorder for Modelsim which takes care of dependency ordering. Is there a feature similar to autoorder from Modelsim in Questa? If so, how can I implement it? Thank you
How to write data in a file from FPGA
Hello, I am a beginner using Quartus and programming FPGA. I need to implement a binary search on FPGA and record the result of the search in a file (a 7 binary code each time). Below is the implementation I did using Quartus and it is synthesizable. I just need help on how to store the D_out, every time the data is ready (valid bit is high).
Failed to access library 'altera_ver' quartus 23.1
Hello, I am new to FPGA's and i am trying to learn to work with them. while i was trying to run an rtl simlation on questasim(free ver) i encountered the following in questasim: # Reading pref.tcl # // Questa Intel Starter FPGA Edition-64 # // Version 2023.3 win64 Jul 17 2023 # // # // Copyright 1991-2023 Mentor Graphics Corporation # // All Rights Reserved. # // # // QuestaSim and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # do inv_run_msim_rtl_verilog.do # vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver # Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023 # vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver # Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver". # No such file or directory. (errno = ENOENT) # Error in macro ./inv_run_msim_rtl_verilog.do line 2 # Questa Intel Starter FPGA Edition-64 vmap 2023.3 Lib Mapping Utility 2023.07 Jul 17 2023 # vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver # Copying C:/intelFPGA_lite/23.1std/questa_fse/win64/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # ** Error (suppressible): (vmap-19) Failed to access library 'altera_ver' at "C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver". # No such file or directory. (errno = ENOENT) # while executing # "error [FixExecError $msg]" # (procedure "vmap" line 29) # invoked from within # "vmap altera_ver C:/intelFPGA_lite/projects/P2/verilog_libs/altera_ver" i can not find anything called altera_ver anywhere. i was getting a different error before which was : C:/IntelFPGA_lite/23.1std/questa_fse/win64/vsim.exe this did not work and after running the quartus # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" tb_inv.v # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs=""+acc"" tb_inv.v # Start time: 12:07:15 on Feb 06,2025 # ** Error (suppressible): (vsim-19) Failed to access library 'tb_inv' at "tb_inv". # No such file or directory. (errno = ENOENT) # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./inv_run_msim_rtl_verilog.do PAUSED at line 12 now iam stuck here for past few hours can you please help me out. i am just trying to run a simple inverter program i have already added the quartus and questa directories to path. i tried to recompile the simulation libraries but there was another error there.
Altera Register Chain
Hello, I'm a student at Georgia Tech. I want to do some timing analysis on flip-flop/register chains. I've read the relevant material for the two devices I have access to - a Cyclone 5 and a Stratix 4. But, even when I manually connect the registers together (top register's q port feeds the bottom register's d port) and constration location assignments, Quartus rearranges how this register works. Most of the time, the simulation is using the asdata port instead of the d port. Chip Planner also shows this transformation happening. This means, I can't actually do the timing analysis I'd like to do. Sometimes it will instead use a lut to feed the flip flop's d port. Both of these situations are ones I'm trying to avoid. I've attempted using generate statements to generate arbitrary shift registers and randomly used logic, but I'm guessing the fan-out is too low to force the router to use the register chain. There's very little information on this feature that's been advertised in multiple devices. I've found one other forum thread about this from 2010, but it didn't really solve anything. Could a moderator provide clarification or a design for the Stratix 4 or Cyclone 5 that makes use the register chain? It's advertised, but I can't get it to synthesize.Platform designer very slow when opening top level system (21.1 Std)
Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have tested it with the same design on multiple machines including: - i7 8700K with 32GB RAM and corporate Windows 10 OS - i9 12900K with 64 GB and corporate Windows 10 OS - i5 7500 with 8 GB RAM and standard Windows 10 OS (to make sure it wasn't the corporate Windows 10 OS) The different hardware didn't seem to make a difference when opening the top level. When opening a subsystem that is instantiated in the top level the Platform Designer doesn't take nearly as long. All of them open within 1 minute and one -taht includes most of the logic - takes about 20minutes to open. When building the whole FPGA it takes 5.5h on the i7 8700K and 3h on the i9 12900K machine. Most of the time is spent in Analysis&Synthesis: the i7 takes about 4h and the i9 2.5h here. I assume that this is caused by the same problem that causes the top level file to be opened so slowly. I have worked on multiple designs with this version of Quartus but have never encountered a similar issue. The project I am currently working on consumes ~80% of the ALM and ~35% of the memory bits in the Arria 10 GX with 270kLE. Unfortunately I cannot share the files themselves due to corporate regulations. Are there any known issues with certain system design choices that can cause the platform designer/quartus to perform so poorly when opening or processing Analysis&Synthesis? Best Regards, FlorianQuartus Prime Lite 23.1 PLL Wizard Problem
Hello, I am a beginner trying to use ALTPLL to generate a PLL IP. The problem is that the MegaWizard quit when I reach the third step "Output Clocks" and don't allow me to continue the IP generation. First image shows the wizard and the step it quits at. Second image shows the menu that appear after the wizard quit, when "yes" is pressed an empty .qip file get added to the project. Am I doing something wrong? please help.
