Diagnosing Congestions
Hello, our Arria 10 design suffers from routing congestions. We used the "Top Congested Nets" report to identify critical nets and reworked the design, e.g. by manual register replication, pipelining etc. Despite the elimination of several high-fan-out nets, routing still fails with congestions. Since we have seen designs containing nets with significantly higher number of overused nodes and fan-outs, we are questioning our metrics. How can we diagnose the root cause of router congestions? Please find attached the archived project. Best regards, NickFritzsche
Unconstrained record support Quartus Prime Standard 23.1 VHDL-2008
I have an array of an unconstrained record: type PinCtrlCfg is record PinMuxSelect : std_logic_vector; EnableOutput : std_logic; end record; type PinCtrlCfgArray is array (natural range <>) of PinCtrlCfg; I'm trying to use it like this: signal Cfg : PinCtrlCfgArray(NUM_OUTPUTS_G-1 downto 0)(PinMuxSelect(toLog2Ceil(NUM_INPUTS_G)-1 downto 0)); This works fine in Questa. However, when trying to synthesize in Quartus, I get the following error message: "object "PinMuxSelect" is used but not declared" VHDL-2008 support is enabled. Unconstrained arrays work fine, but are unconstrained records not supported in Quartus? I'm using Prime Standard 23.1.
