New ContributorHello,
I am a beginner using Quartus and programming FPGA. I need to implement a binary search on FPGA and record the result of the search in a file (a 7 binary code each time). Below is the implementation I did using Quartus and it is synthesizable.
I just need help on how to store the D_out, every time the data is ready (valid bit is high).
Frequent ContributorStore it in a file where? On what device/media? On your Windows PC filesystem? Or on an SDcard attached to your FPGA?
Probably the simplest solution is to dump the data out using a UART serial module and connect the serial pins thru the
appropriate level conversion logic to a USB serial converter plugged into your PC. Then you can capture the result on a terminal window.
New ContributorThank you for the reply.
Storing data in anyway is useful for me. Any way that is easier works for me.
Can you please explain a bit more about the solution you mentioned? What hardware and software I will need to do that?
Frequent ContributorUntil we know what your hardware platform it is hard to be specific.
What FPGA are you using? Is it on a standard development board, or on a custom board of your own design?
What version of Quartus on which platform (Windows, Linux, etc)?
New ContributorFPGA is developement board DE2-115. An I am using Quartus prime 21.1 on Windows.
Frequent ContributorDE2-115 is a very nice development board, I also happen to have one of those.
It has a standard 9p RS232 compatible serial port, so you could just connect that to a PC via a COM port or a SERIAL/USB adapter.
So you could just implement a UART module in the FPGA and write text/data to the serial port and capture it on a PC.
It also has an SDcard socket, but that will require much more effort to use in any effective way.
Same for the etherNet port connections on the board.
New ContributorThanks for the reply.
So I only need to implement UART module in FPGA through Quartus and assign the pin of the module to Rs-232 and connect the R-232 to the PC?
Frequent ContributorCorrect.
In fact you probably only need a UART transmitter module to send data from the FPGA to the PC.
A UART transmitter is the conceptually simpler to implement compared to a UART receiver.
Super ContributorThank you for the quick and helpful suggestions from the community!
Hi @MG007,
Do you need further help in regards to this case?
Best Regards,
Richard Tan
p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.
Super ContributorWe noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support.
We apologize for any inconvenience this may cause and we appreciate your understanding.
If you have any further questions or concerns, please don't hesitate to let us know.
Thank you for reaching out to us!
Best Regards,
Richard Tan
p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.
New Contributormodule BinarySearch (
input logic clk,
input logic [6:0] target,
input logic valid,
output logic [6:0] D_out
);
reg [6:0] result;
integer file_out;
initial file_out = $fopen("output.txt", "w");
always_ff @(posedge clk) begin
if (valid) begin
result <= D_out;
$fwrite(file_out, "%b\n", result);
end
end
endmodule
This shortened version retains the essential components for storing D_out when valid is high and writes the result to a file during simulation. Adjust the file path and name as needed.
Regards
Menupro
Frequent ContributorThe above code snippet will ONLY work within a logic simulation environment.
System tasks like $fopen() $fwrite() $fread() $fclose() etc are not supported in synthesis and on real hardware.
Which was the question the original poster had: saving data from an FPGA design on a physical development board.
New ContributorIf it were me I would use SignalTap with appropriately selected conditional storage qualifiers, then export the data / create signaltap list file.
