MG007
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Re: How to write data in a file from FPGA
Yes, I meant 0xAA or any data. I was also guessing that the enable being one is the issue (just wanted to make sure I am not doing sth wrong), for this testing I used the switches on the FPGA for implementing the enable for transmit. I also wanted to know if there is any software I can use for reading the serial data in PC that I can put the recorded data in excel easily. This one I am using, Serial port monitor, shows the data in a table but does not save it in a table. it only can be saved as text. I need to save the received data like a table in excel.Re: How to write data in a file from FPGA
I again tested the UART transmitted with some constant 8 bit data, and it looks working fine. But I have some other issue to resolve. I am using Serial Port Monitor Software to read the transmitted data, but it reads it continiously in large length. How can I get the data in 8 bits only? For example I sent 01010101 which is "55" in hex and I get this: Or when I sent 10101010 which is "aa" in hex I get this: How I only get 55 or aa only ?Re: How to write data in a file from FPGA
Thank you for the feedback. I tried different data strings, 01010101, 00000000,11111111,10101010,11110000, and 00001111. It seems to work fine. It starts sending bit 0 as starting bit then sending the 8 bit data and sending 1 as ending bit. all 10 bits sent for 435 clk(50M/115200). And it sends data from MSB to LSB.Re: How to write data in a file from FPGA
As I mentioned before, I need to transmit data from FPGA for 7 bit and I need it binary. So I didn't check for characters, only for binary bits. here is waveforms when I sent 01010101. tx_dv should be on to send the data, tx_serial is serial data (PIN_G9). based on the waveform it is sending the each bit data for CLK_PER_BIT (clk/baud rate) times of clk.Re: How to write data in a file from FPGA
I tested the code for UART transmission that I had in modelsim and it looks working fine! (I only tested the transmission, since I only need transmission) I again tested it on FPGA with baud rate of 9600, clk of 50 M and CLKS_PER_BIT = 5208 (BITPER in your code), also with baud rate of 115200, clk of 50 M and CLKS_PER_BIT = 435, but I am still not monitoring the correct data from serial pin! I set the data to be transmitted a constant value in the code for testing purposes. Based on DE2-115 datasheet set the serially out put transmitted data to PIN_G9. Is my pin assignment wrong ? or the parameters?Re: How to write data in a file from FPGA
I am using the clock on the FPGA which is 50 MHz, and baud rate of 115200. based on the code, there is one start bit and one stop bit. (start bit =0, start sending data, and stop bit=1, end of data). Yes I need to test it in ModelSim first. I thought it might be simple since it is only transmitter and I can test it on pga right away.Re: How to write data in a file from FPGA
I think I am doing something wrong. I found this verilog code for UART transmitter online that I used. I wanted to test the transmitter so I set the input data to be controlled by switches on the fpga. I used puTTy as you recommended and also Serial Port Monitor to get the serial data in PC but what I get is not correct. Here is the code for transmitter: module uart_tx #(parameter CLKS_PER_BIT = 44) ( input i_Clock, input i_Tx_DV, input [7:0] i_Tx_Byte, output o_Tx_Active, output reg o_Tx_Serial, output o_Tx_Done ); parameter s_IDLE = 3'b000; parameter s_TX_START_BIT = 3'b001; parameter s_TX_DATA_BITS = 3'b010; parameter s_TX_STOP_BIT = 3'b011; parameter s_CLEANUP = 3'b100; reg [2:0] r_SM_Main = 0; reg [7:0] r_Clock_Count = 0; reg [2:0] r_Bit_Index = 0; reg [7:0] r_Tx_Data = 0; reg r_Tx_Done = 0; reg r_Tx_Active = 0; always @(posedge i_Clock) begin case (r_SM_Main) s_IDLE : begin o_Tx_Serial <= 1'b1; // Drive Line High for Idle r_Tx_Done <= 1'b0; r_Clock_Count <= 0; r_Bit_Index <= 0; if (i_Tx_DV == 1'b1) begin r_Tx_Active <= 1'b1; r_Tx_Data <= i_Tx_Byte; r_SM_Main <= s_TX_START_BIT; end else r_SM_Main <= s_IDLE; end // case: s_IDLE // Send out Start Bit. Start bit = 0 s_TX_START_BIT : begin o_Tx_Serial <= 1'b0; // Wait CLKS_PER_BIT-1 clock cycles for start bit to finish if (r_Clock_Count < CLKS_PER_BIT-1) begin r_Clock_Count <= r_Clock_Count + 1; r_SM_Main <= s_TX_START_BIT; end else begin r_Clock_Count <= 0; r_SM_Main <= s_TX_DATA_BITS; end end // case: s_TX_START_BIT // Wait CLKS_PER_BIT-1 clock cycles for data bits to finish s_TX_DATA_BITS : begin o_Tx_Serial <= r_Tx_Data[r_Bit_Index]; if (r_Clock_Count < CLKS_PER_BIT-1) begin r_Clock_Count <= r_Clock_Count + 1; r_SM_Main <= s_TX_DATA_BITS; end else begin r_Clock_Count <= 0; // Check if we have sent out all bits if (r_Bit_Index < 7) begin r_Bit_Index <= r_Bit_Index + 1; r_SM_Main <= s_TX_DATA_BITS; end else begin r_Bit_Index <= 0; r_SM_Main <= s_TX_STOP_BIT; end end end // case: s_TX_DATA_BITS // Send out Stop bit. Stop bit = 1 s_TX_STOP_BIT : begin o_Tx_Serial <= 1'b1; // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish if (r_Clock_Count < CLKS_PER_BIT-1) begin r_Clock_Count <= r_Clock_Count + 1; r_SM_Main <= s_TX_STOP_BIT; end else begin r_Tx_Done <= 1'b1; r_Clock_Count <= 0; r_SM_Main <= s_CLEANUP; r_Tx_Active <= 1'b0; end end // case: s_Tx_STOP_BIT // Stay here 1 clock s_CLEANUP : begin r_Tx_Done <= 1'b1; r_SM_Main <= s_IDLE; end default : r_SM_Main <= s_IDLE; endcase end assign o_Tx_Active = r_Tx_Active; assign o_Tx_Done = r_Tx_Done; endmodule This is the Quartus modules and pins: This is what I get from using PuTTy: What I get from Serial port Monitor:
