Location: Knowledge Base
40 Results
Why does the Quartus® fail Design Analysis when the 1G/2.5G/5G/10G Multirate Ethernet PHY IP and the F-Tile 1000BASE-KX Ethernet PHY IP are used in the same design?
...P cores in the same project: 1G/2.5G/5G/10G Multirate Ethernet PHY IP (alt_mge_phy) F-Tile 1000BASE-KX Ethernet PHY IP (intel_mge_phy_f) Both IP cores include an RTL module named a...56Views0likes0CommentsWhy is the IP Catalog GUI getting stuck when the Reconfig group parameter value is changed for the F-tile Ethernet Multirate IP?
...aunching the IP Catalog GUI. This problem is seen for the F-tile Ethernet Multirate IP designs. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 25.1.1...161Views0likes0CommentsWhy does the link take long to come up for GTS Ethernet Hard IP with auto-negotiation and link training (AN/LT) multirate designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see link down problem for GTS Ethernet Hard IP with auto-negotiation and link training (AN/LT) multirate...153Views0likes0CommentsWhy does the o_rx_pcs_ready signal fail to assert in hardware for the PAM4 variant of the F-Tile Ethernet Multirate FPGA IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, the o_rx_pcs_ready signal will fail to assert in hardware for the PAM4 variant of the F-Tile Ethern...132Views0likes0CommentsWhy is the “o_rx_pause” width as double as the expected value for 40GE designs when using the F-Tile Ethernet FPGA Hard IP and F-Tile Ethernet Multirate FPGA IP?
...he F-Tile Ethernet FPGA Hard IP and F-Tile Ethernet Multirate FPGA IP. This is due to the quanta value shifted by one extra bit. Resolution To work around this problem, follow the steps below....108Views0likes0CommentsWhy does the FHT “200GE-4 Reconfigurable” F-Tile Ethernet Multirate IP variant fail to transmit ethernet packets after being reconfigured to the 2x100GE-1 or the 2x100GE-2 profiles?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the FHT “200GE-4 Reconfigurable” F-tile Ethernet Multirate IP variant will fail to transmit ethernet...77Views0likes0CommentsWhy am I seeing linkup problem for the GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) multirate IP for HVIO PLL enabled 25G rate designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may see linkup problem for the GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) multirate...45Views0likes0CommentsIs the Aldec Riviera simulator tool suite supported by the F-Tile Ethernet Multirate Intel® FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, the Aldec Riviera simulator tool suite is not supported by the F-Tile Ethernet Multirate Intel® F...159Views0likes0CommentsWhy do I see stability problems with the dynamic reconfiguration design example which uses the F-Tile Ethernet Multirate FPGA IP with FGT PMAs in external loopback?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.3, the dynamic reconfiguration design examples that use the F-Tile Ethernet Multirate FPGA IP in external l...191Views0likes0CommentsWhy does the F-Tile Ethernet Multirate FPGA IP start transmitting invalid packets when the “i_p<n>_tx_rst_n” or “o_p<n>_rst_n” signals are deasserted?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the F-Tile Ethernet Multirate FPGA IP will transmit invalid packets when the “i_p<n>_tx_rst_n” or “o_p&l...102Views0likes0Comments