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MHada's avatar
MHada
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

PAD ON VIA AND 0201 SIZES OF DECAP ON ARRIA 10 SOC DEVELOPMENT KIT

Hi,

We have designed several boards with CYCLONE V SOC and even though if the Kit recommended PAD ON VIAs for the FPGA we went ahead standard layout.

Here on ARRIA 10 SOC Kit, we see PAD ON VIA on FPGA with 0201 sizes of DECAP on BOTTOM Layer.

My query is that for ARRIA 10 SOC - whether a PAD ON VIA is needed or whether we can go with a Standard BGA Fanout and 0402 sizes of DECAPS as normal. This helps us in assembly, reduces PCB complexity, reduces costs, aids maintenance. Search for a reliable PCB manufacturer also becomes a task as we have never done this before.

However, we are aware of the fact that in very high speed designs PDN may improve due to PAD ON VIA and 0201 sizes but various people have various opinions in that regard.

Can you please let us know as to whether this is mandatory to have these two features or whether a standard layout can do. We are using SFP+, SGMII and JESD ADCs for our design.

A reply will be very very helpful here.

8 Replies

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    Thank you for reaching out to Intel FPGA Community.

    Could you mind sharing the document you are referring to?

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    From your question, I would suggest you follow the recommended layout instead of the standard layout because we can't be guaranteed on compatibility with the board. For the size of the DECAP, the suggested size is purposely to have less inductance value of the capacitor. If you can obtain less or the same inductance value with 0421 instead of recommended 0201 then it should be okay.


    • MHada's avatar
      MHada
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Hi,

      As I informed the same was even for CYCLONE V SOC KIT but we went and succeeded with standard layout.

      So how critical can it be for Altera. Any critical analysis of this?

      • MHada's avatar
        MHada
        Icon for Occasional Contributor rankOccasional Contributor
        4 years ago

        I mean ARRIA 10 sorry here in place of Altera

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Yes, I understand that you were succeeded with the standard layout on Cyclone V Soc Kit but with the different type of device family that you are using now which in you case is the Arria 10 Soc Kit, I could not guaranteed on the same success rate you get the same for Cyclone device.


    I try to find the related document on this issue and you may check the link given below:

    Signal Integrity Support Center | Intel



    • MHada's avatar
      MHada
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago
      @AqidAyman_Intel wrote:

      I could not guaranteed on the same success rate you get the same for Cyclone device.

      I try to find the related document on this issue and you may check the link given below:

      Signal Integrity Support Center | Intel

      Hi Aqid,

      Actually I was looking for some specific reasons of the same not working and for that I have floated this question on this group.

      As to whether it is the device or my design requirement which will force me to use PAD ON VIAs which I do not want to use for aforementioned reasons.

      I still wait for that...

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread.

    Thank you.