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MHada's avatar
MHada
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

PAD ON VIA AND 0201 SIZES OF DECAP ON ARRIA 10 SOC DEVELOPMENT KIT

Hi, We have designed several boards with CYCLONE V SOC and even though if the Kit recommended PAD ON VIAs for the FPGA we went ahead standard layout. Here on ARRIA 10 SOC Kit, we see PAD ON VIA o...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

From your question, I would suggest you follow the recommended layout instead of the standard layout because we can't be guaranteed on compatibility with the board. For the size of the DECAP, the suggested size is purposely to have less inductance value of the capacitor. If you can obtain less or the same inductance value with 0421 instead of recommended 0201 then it should be okay.


MHada's avatar
MHada
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi,

As I informed the same was even for CYCLONE V SOC KIT but we went and succeeded with standard layout.

So how critical can it be for Altera. Any critical analysis of this?

  • MHada's avatar
    MHada
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    I mean ARRIA 10 sorry here in place of Altera