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MHada's avatar
MHada
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

PAD ON VIA AND 0201 SIZES OF DECAP ON ARRIA 10 SOC DEVELOPMENT KIT

Hi, We have designed several boards with CYCLONE V SOC and even though if the Kit recommended PAD ON VIAs for the FPGA we went ahead standard layout. Here on ARRIA 10 SOC Kit, we see PAD ON VIA o...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Thank you for reaching out to Intel FPGA Community.

Could you mind sharing the document you are referring to?