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MHada's avatar
MHada
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

PAD ON VIA AND 0201 SIZES OF DECAP ON ARRIA 10 SOC DEVELOPMENT KIT

Hi, We have designed several boards with CYCLONE V SOC and even though if the Kit recommended PAD ON VIAs for the FPGA we went ahead standard layout. Here on ARRIA 10 SOC Kit, we see PAD ON VIA o...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Yes, I understand that you were succeeded with the standard layout on Cyclone V Soc Kit but with the different type of device family that you are using now which in you case is the Arria 10 Soc Kit, I could not guaranteed on the same success rate you get the same for Cyclone device.


I try to find the related document on this issue and you may check the link given below:

Signal Integrity Support Center | Intel



  • MHada's avatar
    MHada
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago
    @AqidAyman_Intel wrote:

    I could not guaranteed on the same success rate you get the same for Cyclone device.

    I try to find the related document on this issue and you may check the link given below:

    Signal Integrity Support Center | Intel

    Hi Aqid,

    Actually I was looking for some specific reasons of the same not working and for that I have floated this question on this group.

    As to whether it is the device or my design requirement which will force me to use PAD ON VIAs which I do not want to use for aforementioned reasons.

    I still wait for that...