Forum Discussion
MHada
Occasional Contributor
Occasional ContributorPAD ON VIA AND 0201 SIZES OF DECAP ON ARRIA 10 SOC DEVELOPMENT KIT
Hi,
We have designed several boards with CYCLONE V SOC and even though if the Kit recommended PAD ON VIAs for the FPGA we went ahead standard layout.
Here on ARRIA 10 SOC Kit, we see PAD ON VIA o...
AqidAyman_Altera
Regular Contributor
Regular ContributorHi,
Thank you for reaching out to Intel FPGA Community.
Could you mind sharing the document you are referring to?
MHadaHi,
Please read me query once again along with this layout file of ARRIA 10 SOC KIT Layout File
