New ContributorMSGDMA ST-to-MM: Linux Driver Necessity & F2SDRAM Path Feasibility
Hello everyone, I am currently working on an MSGDMA implementation. I have verified that I can read the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode.
I have two specific questions regarding this setup:
1、Is configuring the MSGDMA Linux kernel driver a mandatory condition for the hardware to function correctly? Is it possible to bypass the driver and configure the MSGDMA to start data transfer directly using devmem2 (user-space access)?
2、I noticed that some implementations write to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM link, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?
Hello,
- You can configure the MSGDMA IP directly from userspace using devmem2, or with other userspace access technologies such as UIO. For details of how to configure it, including registers, see https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/modular-scatter-gather-dma-core. However please note that you will need to provide the MSGDMA with physical memory addresses to read from and write to - you will need to either pin and map memory areas in the kernel, or reserved physical address ranges in some way (for example https://www.kernel.org/doc/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml)
- The FPGA2HPS bridge is cache-coherent. This means that the state of the cache is kept synchronized with memory operations performed by MSGDMA over the bridge. You may use FPGA2SDRAM instead, however you must manage cache coherency yourself. This is usually done in a Linux kernel driver. I am not aware of any mechanism to achieve this from userspace.
