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drbarryh's avatar
drbarryh
Icon for Occasional Contributor rankOccasional Contributor
7 hours ago

Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA

Greetings all ALTERA Experts,

Can somebody please provide some guidance (e.g. links to example designs and App notes etc.) showing how to implement an mSGDMA based system using a NIOSV/m processor on a MAX10 FPGA?

The first problem is where to find the best and most up to date Documentation and any example designs actually using the mSGDMA. With clear descriptions of how the data and control flow works, hopefully describing how descriptors are created and then used by the mSGDMA IP cores.

Another area of concern is how to wire up mSGDMA IP cores correctly in a Qsys platform (to both data and descriptor memory etc.), and with both the prefetcher and burst mode enabled. I want to use one mSGDMA with an AVALON MM -> AVALON ST flow and a second for AVALON ST -> AVALON MM Flow. 

Then the next area of concern is how to write a HAL based driver with the NIOSV/m processor to interact with mSGDMA IOP cores.

Thanks for any help,

Dr Barry H

 

embedded peripheral
general
Sw Development

6 Replies

  • SueC_Altera's avatar
    SueC_Altera
    Icon for Contributor rankContributor
    7 hours ago

    Hi Dr Barry H,

    I don't see that exact example.  There's a Nios V on Max 10 example here. There's a Nios V with mSGDMA on Agilex 5 here. I wonder if you can use those to figure out what you need to know.  Please let me know.

    Thanks,

    Sue

    • drbarryh's avatar
      drbarryh
      Icon for Occasional Contributor rankOccasional Contributor
      6 hours ago

      Hi Sue,

      Thanks for the 2 links .....but neither seem to be very useful to me to be honest. The first one doesn't show anything about an mSGDMA or any other DMA and i can't see any mention of using an mSGDMA on the Agilex 5 example either, plus i don't have an Agilex 5 Premium board or Quartus Prime Pro (i am working with Quartus Standard edition 25.1 and a MAX10 Development board). Thanks for trying though. I will continue my quest !

      Best regards,

      Dr Barry H

       

  • SueC_Altera's avatar
    SueC_Altera
    Icon for Contributor rankContributor
    6 hours ago

    Hi Dr. Barry H,

    I'm sorry - I thought the DMA was in the Agilex 5 design.  We do have an Agilex 7 design you could adapt to Max 10

    Sue

    • drbarryh's avatar
      drbarryh
      Icon for Occasional Contributor rankOccasional Contributor
      5 hours ago

      Hi Sue,

      No problem.....ALTERA does have a huge database full of just about everything, and i know it is hard to apply the right filters so that you get the right things sometimes (always!).

      Yes please if you can point me to that AGILEX 7 + mSGDMA example design and if i can unzip it and see it in a Platform on Quartus it would help to get me started i hope.

      Cheers, Dr Barry H

  • SueC_Altera's avatar
    SueC_Altera
    Icon for Contributor rankContributor
    5 hours ago

    Hi Dr. Barry H,

    I put the link in my text, but it didn't work! :-(

    It also won't let me just paste the link.  I don't know why!  Paste this link in your brower: 

    https://www.intel.com/content/www/us/en/design-example/843487/agilex-7-nios-v-m-processor-with-ddr-dma-and-ocm-design-example.html

    Sue

    • drbarryh's avatar
      drbarryh
      Icon for Occasional Contributor rankOccasional Contributor
      4 hours ago

      Thanks Sue, yes this text boxing can be picky can't it ! Right the link you sent me worked and i can see an AGILEX 7 example design PAR file and it does at least have DMA in it so that is a better start !

      Thanks for the help, Dr Barry H