Forum Discussion

drbarryh's avatar
drbarryh
Icon for Occasional Contributor rankOccasional Contributor
9 hours ago

Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA

Greetings all ALTERA Experts, Can somebody please provide some guidance (e.g. links to example designs and App notes etc.) showing how to implement an mSGDMA based system using a NIOSV/m processor o...
embedded peripheral
general
Sw Development
SueC_Altera's avatar
SueC_Altera
Icon for Contributor rankContributor
6 hours ago

Hi Dr. Barry H,

I put the link in my text, but it didn't work! :-(

It also won't let me just paste the link.  I don't know why!  Paste this link in your brower: 

https://www.intel.com/content/www/us/en/design-example/843487/agilex-7-nios-v-m-processor-with-ddr-dma-and-ocm-design-example.html

Sue

drbarryh's avatar
drbarryh
Icon for Occasional Contributor rankOccasional Contributor
6 hours ago

Thanks Sue, yes this text boxing can be picky can't it ! Right the link you sent me worked and i can see an AGILEX 7 example design PAR file and it does at least have DMA in it so that is a better start !

Thanks for the help, Dr Barry H