Arria 10 SoC Dev Kit Baremetal HPS examples issue & workflow

Hi Keloke98,

I will be out of office starting next week, thus response will be slower. Please do try to execute the steps to build the uboot till the creation of the sdcard.img , if everything works , you should see that you are using a new uboot version instead of the old one.

Thanks

Regards

Kian

Looks like the old U-Boot 2021.04 version you are using may behave differently. Please use the one I mentioned above, the U-Boot 2025.07. You can get the SD card from https://releases.rocketboards.org/2025.10/gsrd/a10_gsrd/sdimage.tar.gz, and add your application.axf to the FAT partition.

If you prefer a small SD card image, that does not have the kernel and rootfs inside, you can build one by using the instructions below. I have used Ubuntu 22.04, but it should work the same also in WSL:

cd $TOP_FOLDER
sudo rm -rf sd_card && mkdir sd_card && cd sd_card
wget https://releases.rocketboards.org/release/2020.11/gsrd/tools/make_sdimage_p3.py
sed -i 's/\"\-F 32\",//g' make_sdimage_p3.py
chmod +x make_sdimage_p3.py
wget https://releases.rocketboards.org/2025.10/gsrd/a10_gsrd/u-boot-splx4.sfp
mkdir fatfs &&  cd fatfs
wget https://releases.rocketboards.org/2025.10/gsrd/a10_gsrd/fit_spl_fpga.itb
wget https://releases.rocketboards.org/2025.10/gsrd/a10_gsrd/u-boot.img
cp $TOP_FOLDER/intel-socfpga-hwlib/examples/A10/Altera-SoCFPGA-HardwareLib-Timer-A10-GNU/application.axf .
cd ..
sudo python3 ./make_sdimage_p3.py -f \
-P u-boot-splx4.sfp,num=3,format=raw,size=10M,type=A2  \
-P fatfs/*,num=1,format=vfat,size=20M \
-s 32M \
-n sdcard_a10.img

If you want faster iteration time, and not to have to udpate the SD card each time you change something, you can download the application.axf over network, via TFTP. I use Linux, but there are Windows TFTP servers too, for example https://pjo2.github.io/tftpd64/. See below an example of such usage, note that you will have to replace server ip with your own value:

=> setenv autoload no
=> dhcp
Speed: 1000, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
DHCP client bound to address 192.168.1.157 (1011 ms)
=> setenv serverip 192.168.1.101
=> tftp 0x10000000 application.axf
Speed: 1000, full duplex
Using ethernet@ff800000 device
TFTP from server 192.168.1.101; our IP address is 192.168.1.157
Filename 'application.axf'.
Load address: 0x10000000
Loading: ##################
         5.1 MiB/s
done
Bytes transferred = 258864 (3f330 hex)
=> bootelf 0x10000000
=> go 0x00100040
## Starting application at 0x00100040 ...
INFO: Frequency = 300000000.
INFO: Period    = 1500 millisecond(s).
INFO: Counter   = 450000000.
RESULT: Example completed successfully.

I apologize, I was not able to use Ashling RiscFree to succesfully debug either U-Boot or the bare-metal application on the A10 board. I have not used this combination before, so not sure if it is a problem with what I am doing, or something else. 

Note the 25.3 release of Ashling RiscFree installer contains an older version of the tool. You can get the latest available version from the 25.1.1 release at this link: https://www.altera.com/download-center/license-agreement/78291/289e6b3d2979a43f6ddfb46c3eeabfca0b49b3c4?filename=RiscFreeSetup-25.1.1.125-windows.exe.

Will continue after the holidays, in early January. Hopefully someone else can also help in the meantime.

I was, however, able to load and run the application from U-Boot, without a debugger. Here is how you can do that, in case it helps:

1. Compile the HWLIBs design in MSYS2:

# top folder
mkdir a10-baremetal
cd a10-baremetal
export TOP_FOLDER=$PWD

# get hwlibs
cd $TOP_FOLDER
git clone https://github.com/altera-opensource/intel-socfpga-hwlib

# install toolchain
cd $TOP_FOLDER/intel-socfpga-hwlib/tools
./install_linaro.sh
export PATH=$PATH:$PWD/gcc/bin
export CROSS_COMPILE=arm-eabi-

# build the example
cd $TOP_FOLDER/intel-socfpga-hwlib/examples/A10/Altera-SoCFPGA-HardwareLib-Timer-A10-GNU
# fix newlib location
sed -i 's|/local||g' Makefile
# use rm for deleting files
sed -i s'|cs-rm|rm|' Makefile.inc
make clean && make SEMIHOSTED=0 MEMORY=ddr

2. Get the GSRD SD card from https://releases.rocketboards.org/2025.10/gsrd/a10_gsrd/sdimage.tar.gz, extract it and write it to an SD card, for example with https://etcher.balena.io/.

3. Write the  application.axf to the FAT partition of the SD card. You can use Windows for that. Eject card after that.

4. Insert SD card, power up board.

5. Press any key when instructed during countdown, to drop to U-Boot console.

6. Run the following U-Boot commands to load and execute the bare-metal application:

load mmc 0:1 0x10000000 application.axf
bootelf 0x10000000
go 0x00100040

For reference, here is all console output:

U-Boot SPL 2025.07 (Sep 25 2025 - 01:10:31 +0000)
FPGA: Checking FPGA configuration setting ...
FPGA: Start to program peripheral/full bitstream ...
FPGA: Early Release Succeeded.
FPGA: Checking FPGA configuration setting ...
FPGA: Start to program peripheral/full bitstream ...
FPGA: Early Release Succeeded.

U-Boot SPL 2025.07 (Sep 25 2025 - 01:10:31 +0000)
DDRCAL: Success
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 334 ms
FPGA: Checking FPGA configuration setting ...
FPGA: Skipping configuration ...
Trying to boot from MMC1

U-Boot 2025.07 (Sep 25 2025 - 01:10:31 +0000)socfpga_arria10

CPU:   Altera SoCFPGA Arria 10
BOOT:  SD/MMC External Transceiver (1.8V)
Model: Altera SOCFPGA Arria 10
DRAM:  1 GiB
Core:  78 devices, 20 uclasses, devicetree: separate
WDT:   Started watchdog@ffd00300 with servicing every 1000ms (10s timeout)
MMC:   dwmmc0@ff808000: 0
Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Arria 10
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 22:6f:9a:64:64:fe
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0
=>
=> load mmc 0:1 0x10000000 application.axf
258864 bytes read in 15 ms (16.5 MiB/s)
=> bootelf 0x10000000
=> go 0x00100040
## Starting application at 0x00100040 ...
INFO: Frequency = 300000000.
INFO: Period    = 1500 millisecond(s).
INFO: Counter   = 450000000.
RESULT: Example completed successfully.

• GSRD info: https://altera-fpga.github.io/rel-25.3/embedded-designs/arria-10/sx/soc/gsrd/ug-gsrd-a10sx-soc/ 
• GSRD binaries: https://releases.rocketboards.org/2025.10/gsrd/a10_gsrd/ 

$ pacman -S --needed make gcc git

$ git clone https://github.com/altera-opensource/intel-socfpga-hwlib

$ cd intel-socfpga-hwlib/tools

$ ./install_linaro.sh

Hello,

Thank you all for your quick answers, I was finally able to make it work with the  Ashlig RiscFree tool (only with ocr), the issue was on the installation of some of the linaro dependencies, since I'm working on Windows there were some errors during installation, but by manually installing the old toolchain in gcc-arm-8.3-2019.03-i686-mingw32-arm-eabi i was able to make it work.
Your are right about the wrong adress but I sent you with a typo, actually i was trying with ddr.
But now I'm facing another issue while running the Altera-SoCFPGA-HelloWorld-Baremetal-GNU example from HWLIBS, it works fine with ocr:

COMPILER ?= GNU
#COMPILER ?= ARMCC

#MEMORY ?= ddr
MEMORY ?= ocr

#SEMIHOSTED ?= 1
SEMIHOSTED ?= 0

HWLIBS_ROOT := C:/altera_pro/HWLIBS/msys64/home/work/intel-socfpga-hwlib/armv7a/hwlib
NEWLIB_ROOT := C:/intelFPGA/Toolchains/gcc-arm-8.3-2019.03-i686-mingw32-arm-eabi/arm-eabi

ADD_CFLAGS_GNU :=
ADD_CFLAGS_ARMCC :=

EXAMPLE_SRC := hello.c

ELF := application.axf

# These parameters can be overriden
# LINKER_SCRIPT
# HWLIBS_SRC

include Makefile.inc

But not when ddr is selected, while debugging with Ashling I see a lot of empty instructions like if the DDR was not accesible:

         lowlevel_init:
10000000:   andeq   r0, r0, r0
10000004:   andeq   r0, r0, r0
10000008:   andeq   r0, r0, r0
1000000c:   andeq   r0, r0, r0
10000010:   andeq   r0, r0, r0
10000014:   andeq   r0, r0, r0
10000018:   andeq   r0, r0, r0
1000001c:   andeq   r0, r0, r0
          _socfpga_main:
10000020:   andeq   r0, r0, r0
10000024:   andeq   r0, r0, r0
          ___mainCRTStartup_from_arm:
10000028:   andeq   r0, r0, r0
1000002c:   andeq   r0, r0, r0
          _start:
10000030:   ldr     r3, [pc, #76]   @ (0x10000080 <_start+80>)
10000032:   cmp     r3, #0
10000034:   it      eq
10000036:   ldreq   r3, [pc, #68]   @ (0x1000007c <_start+76>)
10000038:   mov     sp, r3
1000003a:   sub.w   r10, r3, #65536 @ 0x10000
1000003e:   movs    r1, #0

Here I modified the start adress of the linker script to test others than the default but the same happened in  0x00100040

OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
	      "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_socfpga_main)
/* Do we need any of these for elf?
   __DYNAMIC = 0;    */
SECTIONS
{
  /* Read-only sections, merged into text segment: */
  . = 0x00100040;
  .vector : { *(.vectors*) }
  .interp     : { *(.interp) 	}
  .hash          : { *(.hash)		}
  .dynsym        : { *(.dynsym)		}
  .dynstr        : { *(.dynstr)		}

If I run the command bdinfo in uboot this is what I get:

=> bdinfo
boot_params = 0x00000100
DRAM bank   = 0x00000000
-> start    = 0x00000000
-> size     = 0x40000000
flashstart  = 0x00000000
flashsize   = 0x00000000
flashoffset = 0x00000000
baudrate    = 115200 bps
relocaddr   = 0x3ff8b000
reloc off   = 0x3ef8afc0
Build       = 32-bit
current eth = ethernet@ff800000
ethaddr     = (not set)
IP addr     = <NULL>
fdt_blob    = 0x3bf830d0
new_fdt     = 0x3bf830d0
fdt_size    = 0x00005e00
lmb_dump_all:
    memory.cnt             = 0x1
    memory.size            = 0x0
    memory.reg[0x0].base   = 0x0
                   .size   = 0x40000000

    reserved.cnt           = 0x1
    reserved.size          = 0x0
    reserved.reg[0x0].base = 0x3bf81ecc
                     .size = 0x407e134
arch_number = 0x00000000
TLB addr    = 0x3fff0000
irq_sp      = 0x3bf830c0
sp start    = 0x3bf830b0
ARM frequency = 1200 MHz
DSP frequency = 0 MHz
DDR frequency = 0 MHz
Early malloc usage: 1544 / 2000

U-Boot SPL 2021.04 (Sep 02 2021 - 08:43:37 +0000)
FPGA: Checking FPGA configuration setting ...
FPGA: Start to program peripheral/full bitstream ...
FPGA: Early Release Succeeded.

U-Boot SPL 2021.04 (Sep 02 2021 - 08:43:37 +0000)
DDRCAL: Success
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 148 ms
FPGA: Checking FPGA configuration setting ...
FPGA: Skipping configuration ...
WDT:   Started with servicing (10s timeout)
Trying to boot from MMC1

By this what I understand is that DDR was correctly initialized and from the original 0x0004_0000 - 0xC000_0000 SDRAM address,  0x0004_0000 - 0x3bf8_1ecc are available to run my code, but then in disassembly I see those empty instructions.
I'm using the precompiled uboot img in Arria10SoCGSRD following your reference, but this is prepared to configure the board to run a linux img not pure baremetal I guess.

Also that I don't understand is that when I use a direction outside that range in the linker script like 0x50000000 the Disassembly code makes sense and seems accesible:

          lowlevel_init:
50000000:   mrc     15, 0, r0, cr1, cr1, {2}
50000004:   orr     r0, r0, #3145728        @ 0x300000
50000008:   mcr     15, 0, r0, cr1, cr1, {2}
5000000c:   mov     r0, #15728640   @ 0xf00000
50000010:   mcr     15, 0, r0, cr1, cr0, {2}
50000014:   mov     r3, #1073741824 @ 0x40000000
50000018:   vmsr    fpexc, r3
5000001c:   bx      lr
          _socfpga_main:
50000020:   bl      0x50000000 <lowlevel_init>
50000024:   b       0x50000028 <___mainCRTStartup_from_arm>
          ___mainCRTStartup_from_arm:
50000028:   ldr     pc, [pc, #-4]   @ 0x5000002c <___mainCRTStartup_from_arm+4>
5000002c:   andpl   r0, r0, r1, lsr r0
          _start:
50000030:   ldr     r3, [pc, #76]   @ (0x50000080 <_start+80>)
50000032:   cmp     r3, #0
50000034:   it      eq
50000036:   ldreq   r3, [pc, #68]   @ (0x5000007c <_start+76>)
50000038:   mov     sp, r3

But at the end I still getting an error which crashes the application and launch back uboot:

Hit any key to stop autoboot:  0 ////////////////(Here I stop manually and launch my code in Ashling ocr works ddr doesnt)
=> data abort
pc : [<5000363a>]          lr : [<5000006d>]
reloc pc : [<1107d67a>]    lr : [<1107a0ad>]
sp : 0007fff0  ip : 00000000     fp : 00000000
r10: 00070000  r9 : 3bf83eb0     r8 : 0000000a
r7 : 00000000  r6 : 00000001     r5 : 00000000  r4 : 50003784
r3 : 00000000  r2 : 00000000     r1 : 50003511  r0 : 00000000
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32 (T)
Code: f243 7484 f2c5 0400 (6825) f8d5
Resetting CPU ...

resetting ...

U-Boot SPL 2021.04 (Sep 02 2021 - 08:43:37 +0000)

Any hint?

The latest available instructions are at https://www.rocketboards.org/foswiki/Documentation/HWLib. That does not use SoC EDS. But it still uses the Arm DS for running the resulted binary.

We also have the Ashlig RiscFree debugger, see https://www.altera.com/products/development-tools/ashling. You can debug A10 bare-metal applications with it. First you could try running up to U-Boot console manually, then download and execute the application with RiscFree. The advantage of RiscFree is that it does not require purchasing a license.

Hi,

Thanks for your feedback. You may need to conver .axf to a Raw Binary .bin file before program it.

you can use fromelf or arm-none-eabi-objcopy to convert it.

1. arm-none-eabi-objcopy -O binary application.axf application.bin
2. copy your application.bin to the board.
3. execute the program.

Hope it helps.