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Occasional Contributor2.5G Ethernet Reference Porting inquiries.
Hi, guys~
My customer wants to use the 2.5G Ethernet feature, but unfortunately, they purchased the Agilex5 Premium Kit instead of the Modular Kit. I am currently following the R&D guide with them, but the 88E2110 is not being recognized properly. Which parts should we check?
First, I followed below link. And have built the Reference Design boot images.
https://altera-fpga.github.io/rel-26.1/embedded-designs/agilex-5/e-series/modular-065b/tsn/sgmii_xcvr_3x2.5G/ug-tsn-sgmii-xcvr-3x2.5G-agilex5/
Second, I regenerated the hardware image after updating the Modular design pinout to match the Premium Kit specs. In the Premium schematic, the 88E2110 PHY reset pin is connected to the FPGA, but there was no control logic applied. So, I added logic to release the reset after 20 ms.
Third, in the device tree, I enabled emac0 and disabled emac1 and emac2.
Since the soft MDIO logic remains unchanged, the addresses shouldn't have changed. However, while the emac0 logs appear, the PHY is still not being recognized. Please refer to the attached boot log. Why did they use soft MDIO instead of the native EMAC0 MDIO? Is this a characteristic of 2.5G Ethernet?
I have completed the porting of the 2.5G Ethernet modular kit design to the premium kit. You can refer to the attached PDF, using AI to translate the Korean text if needed. Anyone in a similar situation who needs to implement 2.5G can refer to this PDF. But Premium Dev Kit doesn't have a PTP chip. So you can use the Ethernet without PTP.
5 Replies
HPark14I have completed the porting of the 2.5G Ethernet modular kit design to the premium kit. You can refer to the attached PDF, using AI to translate the Korean text if needed. Anyone in a similar situation who needs to implement 2.5G can refer to this PDF. But Premium Dev Kit doesn't have a PTP chip. So you can use the Ethernet without PTP.
ChunHsien_AlteraNew Contributor
Good to know that you've got it resolved! Thanks for the update!
I can't find the attached PDF, appreciate if you could attach again for others reference. Thank you!- HPark14
Hi,
I uploaded it again, so go ahead and download it!lease try
- ChunHsien_Altera
Hi,
Can you please take a look at https://altera-fpga.github.io/rel-24.3/embedded-designs/agilex-5/e-series/premium/tsn/sgmii-xcvr/ug-tsn-sgmii-xcvr-agilex5/ which is a 2.5G design released for Agilex 5 ES Premium Devkit? There is very minimal change from ES Premium Devkit to Production Premium Devkit, so this design should be a good reference for the porting effort.
Thanks!
