after pass payload to CRC generator, wireshark do not receive any ethernet frame i guess wrong, i do not know where to check, i am afraid that ethernet port in PC side drop the frame from FPGA when CRC is wrong any other methods to see whether it send or not no matter CRC is wrong or not? which data should be passed to CRC generators, whole ethernet frame? if so, does it include preamble?

What CRC generator are you talking about? If you are using the TSE, it included its own CRC generator. Just send the Ethernet frame without the preample nor CRC.

First I'd appreciate if you could simplify your code and removed all the commented out code lines, it would make it easier to read. Second you still aren't implementing your process right. I have no idea how Quartus will synthesize what you described, but it's probably not what you want. I suggest that you read this document (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) for correct coding styles. A proper clocked process is written like this:process(clock,reset) begin if reset='1' -- initialization code elsif rising_edge(clock) -- or clock'event and clock='1' -- clocked statements end if; end process;This will ensure that Quartus recognises your code as a clocked process and will compile it properly.

which part of data in ethernet frame should be passed to CRC generator?

28 Replies

Altera_Forum
Honored Contributor
12 years ago
I'm sorry I didn't understand either of your questions. The RGMII ports from the TSE need to be connected to the relevant FPGA pins. I don't know what you mean by "data[4]" "data[32]" and "connect with"
Altera_Forum
Honored Contributor
12 years ago
https://skydrive.live.com/redir?resid=e0ed7271c68be47c!345

i got it, it use RGMII to connect the output pin of top layer

back to your previous question, i got no response after press auto analysis in signalTap, and capture a diagram for your reference.

i do not know how to use signaltap, i guess to press programmer transfer the VHDL to chip first and then press cancel the IP Plus messagebox and then press auto analysis in signaltap
Altera_Forum
Honored Contributor
12 years ago
use the first option instead of auto analysis, and this will only run one time. Did you set any trigger?
You musn't cancel the IP plus messagebox, because all your unlicensed cores will stop working. To be able to use evaluation and signaltap at the same time, you need to run one of the two tools (signaltap or the quatrus programmer) separately instead of from the Quartus menu. You will find them in C:\altera\xx.x\quartus\bin (programmer is quartus_pgmw.exe, signaltap is quartus_stpw.exe). Then you can program your FPGA, keep the IP Plus window open, and use signaltap at the same time.

Altera_Forum

Honored Contributor

12 years ago

https://skydrive.live.com/redir?resid=e0ed7271c68be47c!350

https://skydrive.live.com/redir?resid=e0ed7271c68be47c!349

i find it that quite easy to get not compatible error or only can run once after press run then stop

the result is in above picture, i have edited code, is it connection correct? i am using CLOCK_50, why ENET0_TX_CLK do not have 101010 and only 1

and i begin to confused whether using input or output for some pins

where is wrong?

LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity Transmit2 is
  port ( 
         CLOCK_50 : IN STD_LOGIC;
            SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
            
            ENET0_TX_CLK : OUT STD_LOGIC;
            ENET0_TX_DATA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
            ENET0_TX_EN : OUT STD_LOGIC;
            
            ENET0_RX_CLK : IN STD_LOGIC;
            ENET0_RX_DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            ENET0_RX_DV : IN STD_LOGIC
       );
end entity Transmit2;
architecture syn of Transmit2 is
    component tether2 is
      port (  
            ff_tx_data    : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
    
                ff_tx_clk    : IN STD_LOGIC;
                ff_tx_eop    : IN STD_LOGIC;
                ff_tx_sop    : IN STD_LOGIC;
                ff_tx_wren     : IN STD_LOGIC;
        
                read    : IN STD_LOGIC;
                writedata    : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                write    : IN STD_LOGIC;
                clk    : IN STD_LOGIC;
                reset    : IN STD_LOGIC;
                
                --tx_clk    : IN STD_LOGIC;
                
                set_10    : IN STD_LOGIC;
                set_1000    : IN STD_LOGIC;
                ff_tx_crc_fwd    : IN STD_LOGIC;
                
                ff_tx_rdy    : OUT STD_LOGIC;
                
                readdata    : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                ena_10    : OUT STD_LOGIC;
                eth_mode    : OUT STD_LOGIC;
                ff_tx_a_full    : OUT STD_LOGIC;
                ff_tx_a_empty    : OUT STD_LOGIC;
                magic_wakeup    : OUT STD_LOGIC;
                
                tx_clk    : IN STD_LOGIC;
                m_tx_d2 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                m_tx_en2 : IN STD_LOGIC;
                
                rx_clk : IN STD_LOGIC;
                m_rx_d2    : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                m_rx_en2    : IN STD_LOGIC
           );
   end component tether2;
   --
   signal clk_10     : std_logic;
   signal clk_sys    : std_logic;
   signal pll_locked : std_logic;
   signal spi_cs_n   : std_logic;
    
    constant whilelooptrue :STD_LOGIC := '1';
    
    constant enableit : STD_LOGIC := '1';
    constant disableit : STD_LOGIC := '0';
    
    signal set_10_external : STD_LOGIC;
    signal set_100_external : STD_LOGIC;
    
    constant mac: std_logic_vector(47 downto 0) := X"CB90ADD27810";
    constant preamble : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"55"; -- 8 bits * 2 = 16, 4 bits one hex
    constant SFD : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"D5"; -- 8 bits * 2 = 16
    constant dest_mac_addr1 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"10";
    constant dest_mac_addr2 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"78";
    constant dest_mac_addr3 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"D2";
    constant dest_mac_addr4 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"AD";
    constant dest_mac_addr5 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"90";
    constant dest_mac_addr6 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"CB";
    
    constant src_mac_addr1 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"00";
    constant src_mac_addr2 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"12";
    constant src_mac_addr3 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"34";
    constant src_mac_addr4 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"56";
    constant src_mac_addr5 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"78";
    constant src_mac_addr6 : STD_LOGIC_VECTOR (7 DOWNTO 0)  := x"90";
    constant payload : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"4B";
    constant wholepacketlength1 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"00";
    constant wholepacketlength2 : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"20";
    
    constant emptyhex : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"00";
    constant emptytwobits : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
    
    signal tx_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
    signal macaddr_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
    signal CheckSumResult : STD_LOGIC_VECTOR (31 DOWNTO 0);
    signal CheckSumValid : STD_LOGIC;
    
    
    
    signal startpacket : STD_LOGIC;
    signal endpacket : STD_LOGIC;
    signal ff_tx_wren_enable : STD_LOGIC;
    signal ff_tx_rdy : STD_LOGIC;
    signal ena_10 : STD_LOGIC;
    signal eth_mode : STD_LOGIC;
    
    signal ff_tx_a_full : STD_LOGIC;
    signal ff_tx_a_empty    : STD_LOGIC;
    signal magic_wakeup : STD_LOGIC;
    signal beginwrite : STD_LOGIC;
begin
        H1:tether2 port map ( 
                -- Important connection between output pin and TSE
                tx_clk => CLOCK_50,--: IN STD_LOGIC;
                m_tx_d2 => ENET0_TX_DATA,--: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                --m_tx_en2 => ENET0_TX_EN,--: OUT STD_LOGIC
                m_tx_en2 => '1',--: OUT STD_LOGIC
                
                rx_clk => ENET0_RX_CLK, --: OUT STD_LOGIC;
                m_rx_d2 => ENET0_RX_DATA, --: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                m_rx_en2 => ENET0_RX_DV, --: IN STD_LOGIC;
                -- Important connection between output pin and TSE
                
                ff_tx_data    => tx_data,
                ff_tx_clk    => CLOCK_50, 
                ff_tx_eop    => endpacket, 
                ff_tx_sop    => startpacket,
                ff_tx_wren     => ff_tx_wren_enable, 
                
                read    => disableit,
                writedata    => macaddr_data, 
                write    => beginwrite, 
                clk    => CLOCK_50, 
                reset    => disableit, 
                
                --tx_clk    => CLOCK_50,
                
                set_10    => set_10_external,
                set_1000    => set_100_external, 
                ff_tx_crc_fwd    => enableit, 
                
                ff_tx_rdy => ff_tx_rdy, 
                
                ena_10 => ena_10,
                eth_mode    => eth_mode, --0 = 10/100Mbps, 1 = 1000Mbps : OUT STD_LOGIC;
                ff_tx_a_full    => ff_tx_a_full,
                ff_tx_a_empty    => ff_tx_a_empty, 
                magic_wakeup    => magic_wakeup 
        );
    process(CLOCK_50)
    VARIABLE last_clk : std_logic := '0';
    VARIABLE counter : integer := 0;
    VARIABLE last_counter : integer := 0;
    begin
            ENET0_TX_CLK <= CLOCK_50;
            if rising_edge(CLOCK_50) then
                --if SW(0) = '1' then    
                
                if (counter = 0) then
                    ENET0_TX_EN <= '1';
                    
                    
                    beginwrite <= '1';
                    ff_tx_wren_enable <= enableit;
                    
                    macaddr_data <=mac(31 downto 0);
                    
                    startpacket <= enableit;
                    tx_data <= dest_mac_addr1 & dest_mac_addr2 & dest_mac_addr3 & dest_mac_addr4;
                end if;
                if (counter = 1) then
                    macaddr_data(15 downto 0) <=mac(47 downto 32);
                    beginwrite <= '0';
                    startpacket <= disableit;
                    tx_data <= dest_mac_addr5 & dest_mac_addr6 & src_mac_addr1 & src_mac_addr2;
                end if;
                if (counter = 2) then
                    tx_data <= src_mac_addr3 & src_mac_addr4 & src_mac_addr5 & src_mac_addr6;
                end if;
                if (counter = 3) then
                    tx_data <= wholepacketlength1 & wholepacketlength2 & payload & emptyhex;
                    endpacket <= enableit;
                end if;
                if (counter >= 4) then
                    endpacket <= disableit;
                    ff_tx_wren_enable <= disableit;
                    beginwrite <= '0';
                    counter := 0;
                end if;
                last_counter := counter;
                counter := counter + 1;
                --else
                    --beginwrite <= '0';
                --end if;
                last_clk := CLOCK_50;
            end if;
    end process;
 end architecture syn;

Altera_Forum
Honored Contributor
12 years ago
I don't really understand where the '2' in m_rx_d2 and m_rx_en2 is coming from, and why m_tx_en2 is an input.
Except for that, it seems that none of the problems I've listed in post# 8 have been addressed.

Altera_Forum

Honored Contributor

12 years ago

ENET0_TX_DATA do not have data to output to my computer, ENET0_TX_CLK do not have signal like clocking 1 0 1 0 ... , why only 1

i prevent mix up with original m_tx_d, so i rename it to indicate which are output pin

i guess to input tx_data to ff_tx_data

then m_tx_d2 will output to enet0_tx_data, is it correct?

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tether2 IS
PORT ( ff_tx_data    : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        
        ff_tx_clk    : IN STD_LOGIC;
        ff_tx_eop    : IN STD_LOGIC;
        ff_tx_sop    : IN STD_LOGIC;
        ff_tx_wren    : IN STD_LOGIC;
        
        read    : IN STD_LOGIC;
        writedata    : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        write    : IN STD_LOGIC;
        clk    : IN STD_LOGIC;
        reset    : IN STD_LOGIC;
        
        
        set_10    : IN STD_LOGIC;
        set_1000    : IN STD_LOGIC;
        ff_tx_crc_fwd    : IN STD_LOGIC;
        
        ff_tx_rdy    : OUT STD_LOGIC;
        
        readdata    : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        
        ena_10    : OUT STD_LOGIC;
        eth_mode    : OUT STD_LOGIC;
        ff_tx_a_full    : OUT STD_LOGIC;
        ff_tx_a_empty    : OUT STD_LOGIC;
        magic_wakeup : OUT STD_LOGIC;
        
        tx_clk    : IN STD_LOGIC;
        m_tx_d2 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
        m_tx_en2 : OUT STD_LOGIC;
        
        rx_clk : IN STD_LOGIC;
        m_rx_d2    : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        m_rx_en2    : IN STD_LOGIC
       &nbsp;);
END tether2;
ARCHITECTURE Structural OF tether2 IS
    constant enableit : STD_LOGIC := '1';
    constant disableit : STD_LOGIC := '0';
    component tether
      PORT (
        ff_tx_data    : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        ff_tx_eop    : IN STD_LOGIC;
        ff_tx_err    : IN STD_LOGIC;
        ff_tx_mod    : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
        ff_tx_sop    : IN STD_LOGIC;
        ff_tx_wren    : IN STD_LOGIC;
        ff_tx_clk    : IN STD_LOGIC;
        ff_rx_rdy    : IN STD_LOGIC;
        ff_rx_clk    : IN STD_LOGIC;
        address    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        read    : IN STD_LOGIC;
        writedata    : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        write    : IN STD_LOGIC;
        clk    : IN STD_LOGIC;
        reset    : IN STD_LOGIC;
        gm_rx_d    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        gm_rx_dv    : IN STD_LOGIC;
        gm_rx_err    : IN STD_LOGIC;
        m_rx_d    : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        m_rx_en    : IN STD_LOGIC;
        m_rx_err    : IN STD_LOGIC;
        m_rx_col    : IN STD_LOGIC;
        m_rx_crs    : IN STD_LOGIC;
        tx_clk    : IN STD_LOGIC;
        rx_clk    : IN STD_LOGIC;
        set_10    : IN STD_LOGIC;
        set_1000    : IN STD_LOGIC;
        ff_tx_crc_fwd    : IN STD_LOGIC;
        xon_gen    : IN STD_LOGIC;
        xoff_gen    : IN STD_LOGIC;
        magic_sleep_n    : IN STD_LOGIC;
        ff_tx_rdy    : OUT STD_LOGIC;
        ff_rx_data    : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        ff_rx_dval    : OUT STD_LOGIC;
        ff_rx_eop    : OUT STD_LOGIC;
        ff_rx_mod    : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
        ff_rx_sop    : OUT STD_LOGIC;
        rx_err    : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
        readdata    : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        waitrequest    : OUT STD_LOGIC;
        gm_tx_d    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        gm_tx_en    : OUT STD_LOGIC;
        gm_tx_err    : OUT STD_LOGIC;
        m_tx_d    : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
        m_tx_en    : OUT STD_LOGIC;
        m_tx_err    : OUT STD_LOGIC;
        ena_10    : OUT STD_LOGIC;
        eth_mode    : OUT STD_LOGIC;
        ff_tx_septy    : OUT STD_LOGIC;
        tx_ff_uflow    : OUT STD_LOGIC;
        ff_tx_a_full  : OUT STD_LOGIC;
        ff_tx_a_empty : OUT STD_LOGIC;
        rx_err_stat    : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
        rx_frm_type    : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
        ff_rx_dsav    : OUT STD_LOGIC;
        ff_rx_a_full    : OUT STD_LOGIC;
        ff_rx_a_empty    : OUT STD_LOGIC;
        magic_wakeup    : OUT STD_LOGIC
   &nbsp;);
   end component tether;
    
    constant  ENABLE_MAGIC_DETECT: integer :=1;
    constant  ENABLE_MDIO: integer :=0;
    constant  ENABLE_SHIFT16: integer :=1;
    constant  ENABLE_SUP_ADDR: integer :=1;
    
    constant  CRC32GENDELAY: integer :=6;
    constant  MDIO_CLK_DIV: integer :=40;
    constant  ENA_HASH: integer :=1;
    constant  USE_SYNC_RESET: integer :=0;
    constant  STAT_CNT_ENA: integer :=1;
    constant  ENABLE_EXTENDED_STAT_REG: integer :=0;
    constant  ENABLE_HD_LOGIC: integer :=1;
    constant  REDUCED_INTERFACE_ENA: integer :=0;
    constant  CRC32S1L2_EXTERN: integer :=0;
    constant  ENABLE_GMII_LOOPBACK: integer :=1;
    constant  CRC32DWIDTH: integer :=8;
    constant  CUST_VERSION: integer :=0;
    constant  RESET_LEVEL: integer :=1;
    constant  CRC32CHECK16BIT: integer :=0;
    constant  ENABLE_MAC_FLOW_CTRL: integer :=1;
    constant  ENABLE_MAC_TXADDR_SET: integer :=1;
    constant  ENABLE_MAC_RX_VLAN: integer :=1;
    constant  ENABLE_MAC_TX_VLAN: integer :=1;
    constant  SYNCHRONIZER_DEPTH: integer :=4;
    constant  EG_FIFO: integer :=2048;
    constant  EG_ADDR: integer :=11;
    constant  ING_FIFO: integer :=2048;
    constant  ENABLE_ENA: integer :=32;
    constant ING_ADDR : integer  := 11;
    constant  RAM_TYPE: string :="AUTO";
    constant  INSERT_TA: integer :=0;
    constant  ENABLE_MACLITE: integer :=0;
    constant  MACLITE_GIGE: integer :=0;
    constant  MAX_CHANNELS: integer :=0;
    --
    signal gm_tx_d2    :STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";
    signal gm_tx_en2    : STD_LOGIC := '0';
    signal gm_tx_err2 : STD_LOGIC := '0';
    --signal m_tx_d2 : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
    --signal m_tx_en2 : STD_LOGIC := '0';
    signal m_tx_err2    : STD_LOGIC := '0';
    --
    signal ff_rx_data : STD_LOGIC_VECTOR (31 DOWNTO 0) := x"00000000";
    
    constant mac_addr : STD_LOGIC_VECTOR (7 DOWNTO 0) := x"10";--"1078D2AD90CB"; -- address of register stored mac address
    signal ff_tx_mod : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; 
    
    signal rx_err_stat    : STD_LOGIC_VECTOR (17 DOWNTO 0) := "000000000000000000";
    signal rx_frm_type    : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
    
    signal ff_rx_dval2 : STD_LOGIC;
    signal readdata2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
    signal waitrequest2 : STD_LOGIC;
    signal ff_rx_eop : STD_LOGIC;
    signal rx_err : STD_LOGIC_VECTOR (5 DOWNTO 0);
    signal ff_rx_sop : STD_LOGIC;
    signal m_tx_en : STD_LOGIC;
    signal ff_tx_septy    : STD_LOGIC;
    signal tx_ff_uflow    : STD_LOGIC;
    signal ff_rx_dsav : STD_LOGIC;
    signal ff_rx_a_full : STD_LOGIC;
    signal ff_rx_a_empty : STD_LOGIC;
    signal magic_wakeup2 : STD_LOGIC;
BEGIN
H2:tether port map (
            
        ff_tx_data    => ff_tx_data, 
        ff_tx_eop    => ff_tx_eop, 
        ff_tx_err    => disableit, 
        ff_tx_mod    => ff_tx_mod, 
        ff_tx_sop    => ff_tx_sop, 
        ff_tx_wren    => ff_tx_wren, 
        ff_tx_clk    => ff_tx_clk, 
        ff_rx_rdy    => enableit, 
        ff_rx_clk    => ff_tx_clk, 
        address    => mac_addr,
        read    => read, 
        writedata => writedata, 
        write    => write, 
        clk    => clk, 
        reset    => disableit, 
        gm_rx_d    => "00000000",
        gm_rx_dv    => disableit,
        gm_rx_err => disableit, 
        m_rx_d    => m_rx_d2, 
        m_rx_en    => m_rx_en2, 
        m_rx_err    => disableit, 
        m_rx_col    => disableit, 
        m_rx_crs    => disableit, 
        tx_clk    => tx_clk, 
        rx_clk    => tx_clk, 
        set_10    => set_10, 
        set_1000    => set_1000, 
        ff_tx_crc_fwd    => disableit,
        xon_gen    => disableit,
        xoff_gen    => disableit,
        magic_sleep_n    => disableit, 
        ff_tx_rdy    => ff_tx_rdy,
        ff_rx_data    => ff_rx_data, 
        ff_rx_dval    => ff_rx_dval2,
        ff_rx_eop    => ff_rx_eop, 
        ff_rx_mod    => ff_tx_mod, 
        ff_rx_sop    => ff_rx_sop,
        rx_err    => rx_err,
        readdata    => readdata2,
        waitrequest    => waitrequest2,
        gm_tx_d    => gm_tx_d2, 
        gm_tx_en    => gm_tx_en2, 
        gm_tx_err => gm_tx_err2, 
        m_tx_d    => m_tx_d2,
        m_tx_en    => m_tx_en, 
        m_tx_err    => m_tx_err2, 
        ena_10    => ena_10,
        eth_mode    => eth_mode,
        ff_tx_septy    => ff_tx_septy,
        tx_ff_uflow    => tx_ff_uflow,
        ff_tx_a_full    => ff_tx_a_full,
        ff_tx_a_empty    => ff_tx_a_empty,
        rx_err_stat    => rx_err_stat,
        rx_frm_type    => rx_frm_type,
        ff_rx_dsav    => ff_rx_dsav,
        ff_rx_a_full    => ff_rx_a_full,
        ff_rx_a_empty    => ff_rx_a_empty,
        magic_wakeup    => magic_wakeup
       &nbsp;);
        
END Structural;

Altera_Forum
Honored Contributor
12 years ago
If you are sampling in Signaltap with the same frequency than ENET0_TX_CLK then you won't see it changing in Signaltap, it will be a constant 0 or 1. You need to sample at a higher frequency if you want to see anything on that signal. If you are already sampling at a higher frequency then yes, it means you have a problem with ENET0_TX_CLK.
I didn't get how renaming m_tx_d to m_tx_d2 would avoid any mixups. m_tx_d is an output from the TSE core that needs to be connected to the PHY's MII data input ports.
Altera_Forum
Honored Contributor
12 years ago
i wrap TSE in tether2 and connect m_tx_d => m_tx_d2 in order to connect less pins in top layer. output m_tx_d do not have any signal
Altera_Forum
Honored Contributor
12 years ago
From what I'm seeing tether2 doesn't have a m_tx_d output. So instead of renaming it to m_tx_d2 you could keep the m_tx_d name. But anyway, this isn't related to your problem, it's just a matter of code readability.
Altera_Forum
Honored Contributor
12 years ago
yes it has
m_tx_d2 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

if m_tx_d is not output, why it called tx

Forum Discussion

which part of data in ethernet frame should be passed to CRC generator?

28 Replies

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Duplicate_hierarchy_depth / duplicate_register

Automatically added negative node for TDS output doesn't work with Agilex 5