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Altera_Forum's avatar
Altera_Forum
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12 years ago

which part of data in ethernet frame should be passed to CRC generator?

after pass payload to CRC generator, wireshark do not receive any ethernet frame i guess wrong, i do not know where to check, i am afraid that ethernet port in PC side drop the frame from FPGA whe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

https://skydrive.live.com/redir?resid=e0ed7271c68be47c!345

i got it, it use RGMII to connect the output pin of top layer

back to your previous question, i got no response after press auto analysis in signalTap, and capture a diagram for your reference.

i do not know how to use signaltap, i guess to press programmer transfer the VHDL to chip first and then press cancel the IP Plus messagebox and then press auto analysis in signaltap