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Altera_Forum's avatar
Altera_Forum
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12 years ago

which part of data in ethernet frame should be passed to CRC generator?

after pass payload to CRC generator, wireshark do not receive any ethernet frame i guess wrong, i do not know where to check, i am afraid that ethernet port in PC side drop the frame from FPGA whe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If you are sampling in Signaltap with the same frequency than ENET0_TX_CLK then you won't see it changing in Signaltap, it will be a constant 0 or 1. You need to sample at a higher frequency if you want to see anything on that signal. If you are already sampling at a higher frequency then yes, it means you have a problem with ENET0_TX_CLK.

I didn't get how renaming m_tx_d to m_tx_d2 would avoid any mixups. m_tx_d is an output from the TSE core that needs to be connected to the PHY's MII data input ports.