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Altera_Forum
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Honored ContributorVHDL JK FlipFlop Error, Please help
Hello. As you can see in the figure 1, We can make a JK flipflop with 2 ANDs and 2 NORs and two internal signals.
So I've written a very simple code in ModelSim to make and simulate a JK FlipFlop (Figure 2 - the code and Figure 3 - the benchmark which I simulated it in the software) but the problem is, the output of the flipflop is always same. (Figure 4) What is wrong with the outputs? I know there are different ways to make a JK FlipFlop, but this is the way that I should make as a part of an other project, yet I have no clue why the outputs are not working. Fig 1 - click to enlarge: http://www.alteraforum.com/forum/attachment.php?attachmentid=12271&stc=1 Fig 2- click to enlarge: http://www.alteraforum.com/forum/attachment.php?attachmentid=12275&stc=1 Fig 3 - click to enlarge: http://www.alteraforum.com/forum/attachment.php?attachmentid=12273&stc=1 Fig 4 - click to enlarge: http://www.alteraforum.com/forum/attachment.php?attachmentid=12274&stc=119 Replies
Altera_ForumDid you map yoir testbench signals to the ports of your JK entity?
You can also add the i1 and i2 signals to look "inside" th4 flip-flop and see if those change"- Altera_Forum
well as you can see I just mapped the signals in the testbench, there is a question here. should I also port map a signal in the JK code?
- Altera_Forum
Sorry read over your port map.
I don't really see anything wrong in your jk code, but you should not use the type buffer. Use an internal signal for the Q's and then put those on an output. But this is more bad practise than not working code. As for the test bench, which entity do you declare the architecture for? - Altera_Forum
There are 2 errors at the above code:
Note that you defined Q correctly as being resulted from I1 and Qp. However, I2 isn't C and Qp and k, but j instead. The same correction must be done to the other signal. - Altera_Forum
Oh yes, thank you. I corrected that still don't work. This project got canceled.
- Altera_Forum
Your test bench architecture will replace your JK architecture due to identical naming. I would assume you got some warnings loading the project.
- Altera_Forum--- Quote Start --- Your test bench architecture will replace your JK architecture due to identical naming. I would assume you got some warnings loading the project. --- Quote End --- I guess I have never seen a warning while simulating it I actually never paid attention to this while simulating it. But I'm sure there was no warnings while compiling the scripts. But good point, I just corrected that. I think I just did that mistake by editing the file too much. Well after another simulation test and now paying attention to the warnings, nothing changed however I noticed these messages: # vsim -voptargs=+acc work.testshjkff # ** Note: (vsim-3813) Design is being optimized due to module recompilation...# # Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.testshjkff(arch)#1# Loading work.shjkff(arch)#1# Loading work.shjkff(arch)# ** Warning: (vsim-3035) Instantiation depth of '/testshjkff/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF' is 51. This might indicate a recursive instantiation. Increasing limit to 75.# # ** Error: (vsim-3036) Instantiation depth of '/testshjkff/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF/HwshJKFF' is 75. Assuming recursive instantiation.# It's weird that it is instantiating recursively.
- Altera_Forum
Its not weird - you've written :
archtiecture arch of shJKFF is instead of architecture arch of testhsJKFF is this means the architecture in the testbench overrides the one in the JKFF file, which will then call the instantiation recursively. - Altera_Forum
As I mentioned in a sentence before that sentence, I've corrected that mistake. Here is the full testbench code:
http://oi65.tinypic.com/15n95zc.jpg this code gives me those warnings. wierd. Here is the all VHDL files, I'd be glad if someone check them and see if they're working. download here (https://www.mediafire.com/?53t544z55q0hhea) - Altera_Forum
Ive run and tested the code - I dont know what code you're compiling to get the error you are, but I just got an iteration error because Q depends on Qp which depends on Q. The errors you are reporting are because of the old issue. did you forget to recompile the code and restart the simulation?
To make this model correctly, you need to put delays between q and qp, but these are not synthessiable.
