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Altera_Forum
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9 years ago

VHDL JK FlipFlop Error, Please help

Hello. As you can see in the figure 1, We can make a JK flipflop with 2 ANDs and 2 NORs and two internal signals. So I've written a very simple code in ModelSim to make and simulate a JK FlipF...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Sorry read over your port map.

I don't really see anything wrong in your jk code, but you should not use the type buffer. Use an internal signal for the Q's and then put those on an output. But this is more bad practise than not working code.

As for the test bench, which entity do you declare the architecture for?