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Altera_Forum
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9 years ago

VHDL JK FlipFlop Error, Please help

Hello. As you can see in the figure 1, We can make a JK flipflop with 2 ANDs and 2 NORs and two internal signals. So I've written a very simple code in ModelSim to make and simulate a JK FlipF...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Did you map yoir testbench signals to the ports of your JK entity?

You can also add the i1 and i2 signals to look "inside" th4 flip-flop and see if those change"